Browse Prior Art Database

Conversion from Unknown Net Names to Known English Names in Timing Report

IP.com Disclosure Number: IPCOM000116243D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Cheong, H: AUTHOR [+3]

Abstract

Synthesis maps logic equations in the Design System Language (DSL) to technology specific books. The books are called and nets connected together in the VLSI Interactive Design Automation System (VIDAS) TECH. Synthesis changes the net names from recognizable english names entered in the equations to numbered nets.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Conversion from Unknown Net Names to Known English Names in Timing
Report

      Synthesis maps logic equations in the Design System Language
(DSL) to technology specific books.  The books are called and nets
connected together in the VLSI Interactive Design Automation System
(VIDAS) TECH.  Synthesis changes the net names from recognizable
english names entered in the equations to numbered nets.

      The Somerset Timing Evaluator Program (STEP) will flag nets
over the cycle time.  Synthesis has changed the net name from english
such as (MY_NET_IN) to something that can't be correlated easily with
the original name such as (NET1330).  To find out what the
synthesized net name corresponds to requires using a graphical edit
of the timing model to find the bit location and device name of that
net.  Once the location is determined, the DSL file is looked at to
determine the english pin name.

      Namepull provides the logic designer the ability to bypass the
manual work above to get a file that has the synthesized net name
replaced with the english pin name in the cycle time report file
(SLACK) generated by STEP.

Step 1: Namepull reads the SLACK report to gather the nets that have
a synthesized net name.

Step 2: Namepull reads the TECH file to Figure out which bit and
device the synthesized net belongs to.

Step 3: Namepull uses the step 2 list and the compilation of the DSL
(SYN) to get the english pin name for the synthesized net name.  The
english pin name replaces the synthesized net name in the SLACK
report shown b...