Browse Prior Art Database

Checking Graphs for Soft Structures

IP.com Disclosure Number: IPCOM000116246D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Fentanes, J: AUTHOR [+2]

Abstract

The disclosed program checks that the signal pin name inside the graph is the same as the signal wire name outside the graph.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 96% of the total text.

Checking Graphs for Soft Structures

      The disclosed program checks that the signal pin name inside
the graph is the same as the signal wire name outside the graph.

      The new Design System Language (DSL) compiler has introduced
the concept of graphing io pins of a file.  The signal pin name
inside the graph can be named differently than the signal wire name
outside the graph for hard boundaries.  (RLM, DEVICE) An example is
shown below:
  XXX_CLOCK_IN (wire name).......| CLKG (signal pin name) |

      Soft boundaries (MRGOTS, SOFT) must have the same wire name and
signal pin name.  The compiler does not enforce this restriction,
therefore, this program is created to fulfill that need.

Step 1: Graphcheck reads the file list for a given design to
determine what type (i.e., SOFT, RLM) the graph is.

Step 2:  Hard boundaries such as RLM and DEVICE will not be checked
since the wire name and signal pin name are allowed to differ.
Graphcheck compares the wire name and signal pin name for the soft
boundaries.  If the two are different, graphcheck will generate an
error message showing the two signals.

      Graphcheck saves the logic designer from documenting every wire
name change required to fix a simulation bug quickly.  Once the DSL
is ready to continue in the methodology, graphcheck is run to clean
up the wire and signal pin name differences.  The rest of the
methodology
can be run with confidence that all problems due to a mismatch
between a
...