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Differential Driver with Variable Output Pulse Widths

IP.com Disclosure Number: IPCOM000116254D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 6 page(s) / 148K

Publishing Venue

IBM

Related People

Atallah, FI: AUTHOR [+3]

Abstract

To increase the storage density on an optical disk, it is necessary to drive the laser with very accurately controlled pulses. Various pulse widths are required depending on Read, Write, or Erase functions being performed on the disk. Following is the description of the design.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 44% of the total text.

Differential Driver with Variable Output Pulse Widths

      To increase the storage density on an optical disk, it is
necessary to drive the laser with very accurately controlled pulses.
Various pulse widths are required depending on Read, Write, or Erase
functions being performed on the disk.  Following is the description
of the design.

      A block diagram of this design is shown in Fig. 1.  A Phase
Locked Loop (PLL) is used to generate control voltages for PFET and
NFET CMOS devices.  The design of the PLL will not be described in
this design as PLLs are well known to VLSI designers.

      These control voltages are inputs to a delay line of 65 stages.
The control voltages vary such that the delay of each stage is 0.5 ns
for all combinations of process parameters, power supply voltage, and
temperature.  Fig. 2 shows the circuit diagram of the delay stage.
An inverter (devices Q5 and Q6) provide a 'TAP' output from each
stage in the delay chain.  The inverter provides a constant load to
each stage of the delay chain so that variations in the capacitance
loading on each tap will not effect the delay of that stage.

      Three inputs to this invention, PO, P1, and P2 determine the
width of the output pulse from the differential driver.  The
following
table shows the required pulse width for each P0 and P1 combination.
                  P0   P1   P2   output pulse width
                    0    0    1        8.5 ns
                    0    1    1       10.0 ns
                    1    0    1       15.0 ns
                    1    1    1       20.0 ns
                    X    X    0       no pulse    X = don't care

      Fig. 3 shows a block diagram of the decode logic.  On the
rising edge of the clock, inputs P0, P1, and P2 are transferred to
the outputs of the latches.  Random logic circuits decode the latch
outputs per the truth table to generate the outputs gate85, gate10,
gate15, and gate20.  A variety of pulses with different widths can be
provided by increasing the number of inputs and changing the decode
scheme accordingly.

      Only a description of the 10 nsec will be described since all
other pulses are generated similarly.  Fig. 5 shows the schematic of
the control and the differential driver circuitry.  The differential
driver is an open DRAIN driver with external resister loads to match
the impedance of the cable.  Four cross-coupled NANDS (AIs) form two
SET-RESET flip-flops that turn on and off the differential driver.
The falling edge of the SET pulse turns it on, while the falling edge
of the RESET pulse turns it off.  It is important to have identical
layouts of the NANDS to insure that the turn on delay equals the turn
off delay.  Any mismatch would be translated in pulse width
distortion.  The output...