Browse Prior Art Database

Cascaded Memory Array Test Simplification Via Use of Data Bypass

IP.com Disclosure Number: IPCOM000116259D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 110K

Publishing Venue

IBM

Related People

Cho, JB: AUTHOR [+3]

Abstract

In large custom designs, it is necessary to provide a means to test individual areas of the design to determine functionality of the entire chip and also to be able to better isolate failures. Register files or memory arrays are especially difficult since they require large numbers of operations to fully test one device. Existing practice requires a register ahead of the register file or memory array to provide the stimulus for testing, and one register after the register file or memory array to sample the test results. An enhanced alternative is proposed in what follows.

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Cascaded Memory Array Test Simplification Via Use of Data Bypass

      In large custom designs, it is necessary to provide a means to
test individual areas of the design to determine functionality of the
entire chip and also to be able to better isolate failures.  Register
files or memory arrays are especially difficult since they require
large numbers of operations to fully test one device.  Existing
practice requires a register ahead of the register file or memory
array to provide the stimulus for testing, and one register after the
register file or memory array to sample the test results.  An
enhanced alternative is proposed in what follows.

      Another method for testing register files or memory arrays is
to make each storage element within the structure a scannable device.
This approach may be too expensive in the circuit area and ultimately
will negatively impact circuit performance.

      Fig. 1 illustrates three cascaded non-scannable memory arrays
using the prior art for testing.  Note that a multiplexer and a
register are added between the stages of memory arrays.  The register
is provided to capture the test results from the previous stage and
to hold the stimulus for the following memory array.  The multiplexer
is needed to provide a path from the test register to the input of
the following memory array.  The multiplexer and register are only
used for test purposes and so are additional cost in terms of circuit
size, power and performance.

      This invention removes the need for the additional registers
and multiplexers added between the stages of register files or memory
devices and thus, reduces circuit size, power and optimizes circuit
performance.

      The diagram for the proposed new way to test cascaded memory
arrays is shown in Fig. 2.  Here register 1 is used to provide all
data inputs during the normal functioning mode and during test.
Register 2 is used to latch all the data that comes out of the memory
arrays during both normal and test modes.  This simplification is
made possible by putting a bypass feature in the memory arrays.

      The bypass feature is put into the memory array by building a
MUX into the sense amplifier circuit.  An example of how to do this
is shown in Fig. 3 but there are other ways to do this.  The bottom
line is that when the select for the MUX is put i...