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Grouping of Instructions

IP.com Disclosure Number: IPCOM000116288D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 150K

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This disclosure proposes techniques for grouping instructions for indivisible executions. They can achieve complicated atomic executions with simple instructions, as recognizable to the hardware.

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Grouping of Instructions

      This disclosure proposes techniques for grouping instructions
for indivisible executions.  They can achieve complicated atomic
executions with simple instructions, as recognizable to the hardware.

      In current computer architectures each instruction is decoded
and executed individually according to certain sequencing.  For
operations requiring atomic read/write special instructions (e.g.,
Test-and-Set, Compare-and-Swap) are provided to guarantee indivisible
executions.  Such atomic instructions are usually used for coding
software critical regions, though a complex instruction like
Compare-and-Swap itself can perform non-locking type atomic
operations (e.g., linked list manipulation).  In a RISC environment,
there have been proposals for locking with simpler instructions.  An
example is the reservation scheme (via load-and-reserve and
conditional-store instruction pairs).  Such reservation scheme can be
used to implement critical region type locking.  Generally speaking,
when multiple instructions are to be executed with atomicity,
conventional architectures require software to perform locking type
operations in order to execute these instructions in a critical

      This invention proposes the concept that multiple (individually
decoded and executed) instructions be group such that their
executions are logically related as an integral operation and that
such integrity is recognizable by the processor hardware (e.g.,
instruction decoding unit).  For instance, the instructions within a
group may be considered indivisible or atomic as far as memory status
is concerned.  One benefit of the concept is to allow atomic
execution of multiple instructions without explicit semaphore
management.  It also allows a more complex instruction to be broken
into simpler instructions while still maintaining integrity among
them.  The identification of indivisible grouping is up to particular
architecture designs.  Generally speaking, allowing the processor
hardware to directly recognize atomicity of multiple instructions
will offer more flexibility in optimizing the executions.  (It is
"hard" for the hardware to recognize critical regions coded with
software semaphores).

Some examples of instruction grouping are:
  1.  Consider an instruction sequence performing Test-and-Set type
       operations within a RISC type load/store architecture:
      TS:  LOAD      R1,A        load R1 with a word from address A
           LTR       R1,R1       load R1 to itself and test value
           BNZ       $+8         do next instruction only if R1=0
           ST        R2,A        store a (non-zero) value to A

    These four instructions intend to provide a semaphore
implementation for critical regions.  However, even with
write-synchronous architecture (e.g., as in IBM/390*) the
atomicity of execution c...