Browse Prior Art Database

Low-Power Memory Cell for Bipolar Masterslice

IP.com Disclosure Number: IPCOM000116290D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Chu, SG: AUTHOR [+7]

Abstract

Disclosed is a memory cell design in a bipolar Masterslice (MS) which dissipates very low-power, yet operates at high performance.

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This is the abbreviated version, containing approximately 99% of the total text.

Low-Power Memory Cell for Bipolar Masterslice

      Disclosed is a memory cell design in a bipolar Masterslice (MS)
which dissipates very low-power, yet operates at high performance.

      The disclosed cell is a seven transistor design, which is
implemented in a masterslice chip, with a given set of resistor
components to augment the seven transistors in the cell.  The design
offers a two port operation, one read, and one write, and was
produced on a high-end air cooled system's offering.  The design has
high performance, very small size, and dissipates a very small amount
of power.  In addition, the design has an acceptable amount of
stability which protects against particle disturbances.

      The circuit design for the low-power two-port memory cell can
be seen in the Figure.  T2, T4, R2, and R3 comprise the storage cell,
with R1 acting as a level shift, and R4 as a source resistor.
Capacitors C1 and C2 act as stability capacitors, to help maintain
the stored state in charge.  T7 acts a read select device in
conjunction with an external current source, and the two sense
resistors, T1, and T6, which amplify the cell differential to the
sense amp differential circuit.  When the write line is raised,
either T2 or T5 will transfer the difference of the write input
circuit to the cell, and cause the cell to set to the required state.

      The cell and the entire array performed, at least as well as
designed, in the product with no problems encounter...