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Browse Prior Art Database

Device Driver to I/O Device Locking Mechanism

IP.com Disclosure Number: IPCOM000116302D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 91K

Publishing Venue

IBM

Related People

Arndt, RL: AUTHOR [+5]

Abstract

The Peripheral Component Interconnect (PCI) bus contains a protocol for locking sections of system memory on the backside of the

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This is the abbreviated version, containing approximately 53% of the total text.

Device Driver to I/O Device Locking Mechanism

      The Peripheral Component Interconnect (PCI) bus contains a
protocol for locking sections of system memory on the backside of the

PCI

Host

Bridge

(PHB).  This locking mechanism is used by the device
to lock the processor from getting at 16 or more bytes of system
memory (minimum specified in the PCI spec is 16 bytes; bridges can
implement larger granularities but not smaller ones).  For this to be
useful, the processor also has to have a way to lock the device from
getting at that same section of system memory.

Some processors do not have a locking mechanism that allows the
software to lock 16 bytes or more of system memory; at least
directly.  The following information describes a way to implement a
locking mechanism which is external to the processor.  It provides a
method by which device drivers and hardware I/O devices can lock each
other from accessing the same section of shared system memory even
when the processor has limited locking capability.  This mechanism is
applicable to a uniprocessor or to multiprocessor systems.  This
mechanism is also applicable to other I/O buses which have locking
mechanisms which are not directly supportable by the host processor.
The Figure illustrates the logical view of the mechanism.  In this
protocol, a specific device driver utilizes the Load and Store
instruction to temporarily reserve exclusive access to shared areas
in system memory (shared with the same specific master), blocking
that master until the reservation is released by the device driver.
The Load and Store instructions are not used in the conventional
processor sense, but are used as commands directed to the PHB (the
PHB intercepts and executes this special Locking protocol).

The master on the PCI bus utilizes the LOCK# signal to gain exclusive
access to shared areas of system memory (shared with its device
driver), blocking the device driver until released by the master.
  PROTOCOL DESCRIPTION
  Device Driver
  - In accessing shared memory, the device driver utilizes Load and
     Store, and begins with Load.
  - The PHB recognizes t...