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Browse Prior Art Database

Computer Memory Testing using an AC Write Disturb Test

IP.com Disclosure Number: IPCOM000116306D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Sarkany, EF: AUTHOR

Abstract

Disclosed is an AC write disturb test designed to check for AC write-through disturbs in computer memory chips. This test uses a unique three dimensional model of the memory which detects faults not detected by tests using the common two dimensional model. The signal timings to the array are set up to stress the product beyond its worst-case limits. This guarantees against possible failure after extended use.

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This is the abbreviated version, containing approximately 65% of the total text.

Computer Memory Testing using an AC Write Disturb Test

      Disclosed is an AC write disturb test designed to check for AC
write-through disturbs in computer memory chips.  This test uses a
unique three dimensional model of the memory which detects faults not
detected by tests using the common two dimensional model.  The signal
timings to the array are set up to stress the product beyond its
worst-case limits.  This guarantees against possible failure after
extended use.

      This test uses the concept of a "home" address, around which
the rest of the test sequence revolves.  In this case, the physical
organization of the 1Kx9 memory was 128x8x9, i.e., the nine data bits
were assigned to sections of 128 words by eight columns.

      To achieve the correct pattern, one can think of the memory as
a three-dimensional array, made up of eight planes which contain 128
nine-bit data words.  When writing a data word to the array, one of
the eight planes is chosen, one of the 128 entries is addressed, and
the nine bits of data are loaded.  For each loop, data is written
into the home address, and then every address following the home
address and before the home address is written with the opposite
data.

The steps of the test are as follows:
  o  Step 1: Select a plane and load it with a background pattern of
      all ones in every address.
  o  Step 2: Using address 0 as the home address, write zeroes to
this
      address, then write ones to all...