Browse Prior Art Database

CMOS Word Line Decoder for Dense Semiconductor Memories

IP.com Disclosure Number: IPCOM000116307D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 6 page(s) / 209K

Publishing Venue

IBM

Related People

Diniz, GF: AUTHOR [+2]

Abstract

The word line decoders used in any semiconductor memory are typically built from NAND/NOR style base circuits. These circuits typically have strong area, power and performance requirements placed on them so that efficient/optimum memory designs can be realized. This disclosure describes a circuit topology that uses an OR logic function and a one of two selection stage that is driven from the True and Complement of the "Most Significant Bit" (MSB) of the input address. Use of this approach, would allow the building of a M-word memory with M/2 decoder cells, where the two neighboring words are selected by the state of the MSB. Moreover, this implementation can be used in memories with simple clocking schemes, where other similar decoder circuit approaches have more elaborate requirements.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 31% of the total text.

CMOS Word Line Decoder for Dense Semiconductor Memories

      The word line decoders used in any semiconductor memory are
typically built from NAND/NOR style base circuits.  These circuits
typically have strong area, power and performance requirements placed
on them so that efficient/optimum memory designs can be realized.
This disclosure describes a circuit topology that uses an OR logic
function and a one of two selection stage that is driven from the
True and Complement of the "Most Significant Bit" (MSB) of the input
address.  Use of this approach, would allow the building of a M-word
memory with M/2 decoder cells, where the two neighboring words are
selected by the state of the MSB.  Moreover, this implementation can
be used in memories with simple clocking schemes, where other similar
decoder circuit approaches have more elaborate requirements.  The
circuit also lends itself to expansion to handle wider address input,
due to the OR function.

      The function of a word line decoder in a memory is to take a
N-bit address and generate 2-to-the-N unique signals, where each
active signal enables a single word during a read or write operation;
refer to Fig. 1 for memory block diagram and Fig. 2 for basic decoder
block diagram.  A basic decoder can be built with NANDs or NORs, with
each gate having N+1 inputs.  The number of inputs being the width of
the input address plus a clocking signal.  Using this approach, there
would be a decoder for each word.  Each NOR/NAND decoder would then
have the appropriate True or Complement version of the address bits
connected so that 2-to-the-N unique outputs will result.  This
implementation while quite functional, is not a area efficient as
other possible solutions.  The invention disclosed by [*]
illustrates a different decoder circuit topology.  This circuit is
shown in the schematic of Fig. 3.  The operation of this circuit
proceeds as follows: node A is first precharged to Vdd through PFET
P0.  The lower address True/Complement inputs are then applied to the
circuit, shown as A1 - An and the MSB A0 and its complement are
applied to the sources of PFETS P1 & P2.  If the address inputs are
such that the NFETs N4 - Ni are off, then node A stays at Vdd and
node B remains at zero volts.  With node B at ground, both P1 & P2
have the opportunity to turn on.  This is determined by whether the
True or the Complement signal of the MSB is at Vdd (logic '1').  If
A0 is the signal that rises to Vdd, then the output of the inverter
formed by P1/N1 rises from ground to Vdd.  This signal is the
buffered producing the final word line enable signal.  While A0 is at
Vdd, the complement is at zero volts keeping the output of P2/N2 at
zero volts thereby keeping that word line deselected.  After a
predetermined delay, a reset signal rises to Vdd turning on NFET N3
which pulls node A to ground.  This causes node B to rise to Vdd
turning on N1 & N2.  Nodes C & D are pulled to ground turning...