Browse Prior Art Database

Complete Directory for System Memory in Multiprocessor Systems

IP.com Disclosure Number: IPCOM000116309D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Hicks, D: AUTHOR [+2]

Abstract

In a directory-based cache coherence MultiProcessor (MP) system, each memory module is associated with a memory directory to keep track of the presence of its lines in any caches. Each line being used, i.e., loaded to a cache, is represented by an entry in the directory. The directory provides a fast way to locate a missing line and can serialize any concurrent accesses to a memory location in the MP system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Complete Directory for System Memory in Multiprocessor Systems

      In a directory-based cache coherence MultiProcessor (MP)
system, each memory module is associated with a memory directory to
keep track of the presence of its lines in any caches.  Each line
being used, i.e., loaded to a cache, is represented by an entry in
the directory.  The directory provides a fast way to locate a missing
line and can serialize any concurrent accesses to a memory location
in the MP system.

      When the number of processors, i.e., n, is not very large, a
simple implementation is to keep in the memory directory an entry
with a tag and a bit vector of n for each cache line being used: bit
i in the vector indicates the presence of the line in the cache of
CPU i.  However, when there is an I/O bus connected to each
processor, the above approach requires at least 2n presence bits per
entry so that the presence of a cache line in a CPU's cache or the
cache of the attached I/O device(s) can be correctly distinguished.

      A scheme is disclosed which requires only n+2 presence bits
(instead of 2n bits) per entry for all the cache lines in the system,
including those of the attached I/O devices to the processors in an
MP system.  An entry in the directory consists of a tag, a presence
bit for each CPU in the system, and an exclusive bit, E, which
indicates if the presence is unique among all the caches in the
system.  In particular there are two bits: IOPE1 and IOPE2, which are
operated in the following ways:
  1.  The two IOPE bits represent the presence of the cache line in
the
       cache of an I/O device or the processor's cache.  It is
assumed
       that there can be multiple I/O devices connected to an I/O bus
       and each device can have a cache.  A request presented at the
bus
       contributes a bus snoop to the cache(s) attached to the bus,
or
       the request is presented to a router, e.g., the router can be
       part of the bus controller which is able to locate the
requester
       of a line or the device(s) where a cache line is stored.  To
this
       regard, multiple caches connected to the IO bus of a processor
is
       consid...