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Timing Multi-Cycle Paths with a Single Cycle Clock

IP.com Disclosure Number: IPCOM000116314D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Okpisz, A: AUTHOR [+2]

Abstract

Previously, multi-cycle paths were so few in number that the timing engineer conferred with the logic designer to determine the multi-cycle signals that had to be adjusted for the extra cycles needed to complete the path.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 76% of the total text.

Timing Multi-Cycle Paths with a Single Cycle Clock

      Previously, multi-cycle paths were so few in number that the
timing engineer conferred with the logic designer to determine the
multi-cycle signals that had to be adjusted for the extra cycles
needed to complete the path.

      The new clocking strategy has created a multi-cycle path for
any signal that is on a clocking boundary that is slower than the
fastest clock.  The logic designer knows the clocking requirements of
the logic, but has no way of putting that information into the logic
until now.

      Instead of the logic designers spending time discussing timing
adjusts with the timing engineer, they can now stipulate the
multi-cycle signals in their logic.  The timing adjusts will
automatically be created in the timing model.  Timing of the
structure will be accurately modeled without the intervention of the
timing engineer.

      Step 1: Logic designers determine the multi-cycle signals for a
given clock ratio and group them into storage elements.  A keyword
such as DIVIDER=4 is used to give the ratio of the multi-cycle clock
to the fastest clock.  An example would be:
  DEVICE  SOA0: LATCH(TYPE=1, WIDTH=13: DIVIDER=4)

      Step 2: Compilation and weaving of the logic bring the keyword
into the Virtual In-core Model (VIM).

      Step 3: The timing program read the VIM.  The keywords cause a
timing adjust to be placed on all data input signals of that storage
element.  Norm...