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Resistive Load Metal Oxide Semiconductor Amplifier using Distributed Diffusion Resistance

IP.com Disclosure Number: IPCOM000116318D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 64K

Publishing Venue

IBM

Related People

Mullen, JM: AUTHOR

Abstract

Disclosed is a method of using the parasitic diffusion resistance as the load element in a Metal Oxide Semiconductor (MOS) amplifier. A typical resistor load MOS amplifier is shown in Fig. 1. R1 = load resistor, (W/L) = transistor size, kn = device transconductance, and Id = bias current.

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Resistive Load Metal Oxide Semiconductor Amplifier using Distributed
Diffusion Resistance

      Disclosed is a method of using the parasitic diffusion
resistance as the load element in a Metal Oxide Semiconductor (MOS)
amplifier.  A typical resistor load MOS amplifier is shown in Fig. 1.
  R1 = load resistor, (W/L) = transistor size, kn = device
transconductance, and Id = bias current.

      Where Cload=load capacitance.  Cload is caused by the parasitic
associated with the diffusion of the MOS device as well as the
parasitic associated with the load resistor.

      Fig. 2 shows the same amplifier as Fig. 1 with a different
layout.  The new layout uses the parasitic associated with the
diffusion of the MOS device as distributed load resistance.  Fig. 2
also shows the distributed schematic with n elements (n is large),
and the effective schematic.

      To analyze the gain of the distributed schematic in Fig. 2,
superposition can be used.

      Equation 6 shows the gain is reduced by a factor of 2 over the
typical MOS amplifier.  However, the chip area has been reduced and
the amplifier bandwidth has been increased.  The bandwidth has been
increased because Cload now only consists of the parasitic associated
with the diffusion of the MOS device.