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Browse Prior Art Database

Handle Generation Algorithm

IP.com Disclosure Number: IPCOM000116323D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Berkoff, RA: AUTHOR [+2]

Abstract

Disclosed is an algorithm for generating 32-bit handles having several desirable properties. These handles, which can be directly translated into meaningful storage addresses without an extensive table search, are sufficiently randomized to make the possibility of the undetected reuse of an invalidated handle remote, and are encrypted so that their underlying meaning is not readily apparent to their recipient. A provision is also made for the use of predefined "pseudo-handles."

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This is the abbreviated version, containing approximately 54% of the total text.

Handle Generation Algorithm

      Disclosed is an algorithm for generating 32-bit handles having
several desirable properties.  These handles, which can be directly
translated into meaningful storage addresses without an extensive
table search, are sufficiently randomized to make the possibility of
the undetected reuse of an invalidated handle remote, and are
encrypted so that their underlying meaning is not readily apparent to
their recipient.  A provision is also made for the use of predefined
"pseudo-handles."

      The Figure shows the layout of a 32-bit handle generated by the
algorithm.  A global variable is incremented each time a handle is
allocated, and the 14-bit Sequence Number is generated by taking the
value of this variable modulo 16,384, where 16,384 is equal to the
number two raised to the fourteenth power.  The Sequence Number is
shifted to the position shown in the Figure.  Since a Sequence Number
field of all 'ones' is reserved for pseudo-handles, such a Sequence
Number is rejected if it is calculated in this way, with a new
Sequence Number being generated as the global variable is again
incremented.  The 16-bit Storage Pool Offset field is generated by
the low-order 16 bits of the address of the storage object to which
the handle refers.  The 2-bit Storage Pool Id is used to replace the
high-order bits of the storage address.  Up to four distinct
selectors, or 64KB linear address ranges can be accommodated through
this layout.

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