Browse Prior Art Database

Digital Phase-locked Loops using Shared Logic, Accepting Variable Reference and System Clocks

IP.com Disclosure Number: IPCOM000116342D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 6 page(s) / 187K

Publishing Venue

IBM

Related People

Davis, GT: AUTHOR [+2]

Abstract

A method for generating several clocks phase-locked to a reference clock is disclosed. The scheme permits generation of fixed phase-locked frequencies from variable reference frequency and variable system clock frequency. The phase-locked loops utilize shared logic. The phase-locked loop scheme described here generates several clocks, each phase-locked to a common reference clock. The scheme can generate fixed output frequencies with a variety of reference and system clocks. The invention is described in terms of a specific implementation, but is not limited to that implementation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 25% of the total text.

Digital Phase-locked Loops using Shared Logic, Accepting Variable
Reference and System Clocks

      A method for generating several clocks phase-locked to a
reference clock is disclosed.  The scheme permits generation of fixed
phase-locked frequencies from variable reference frequency and
variable system clock frequency.  The phase-locked loops utilize
shared logic.  The phase-locked loop scheme described here generates
several clocks, each phase-locked to a common reference clock.  The
scheme can generate fixed output frequencies with a variety of
reference and system clocks.  The invention is described in terms of
a specific implementation, but is not limited to that implementation.

      The invention described here and shown in Fig. 1 solves these
problems efficiently by sharing logic.  A conventional solution to
this problem would utilize a separate reference counter and ring to
generate each output frequency.  This invention modifies the
reference counter and ring slightly, so that one reference counter
can be used to synchronize all the rings.

      The reference counter counts the reference clock down to the
phase comparison frequency in a manner that can be used by all the
phase-locked loops.  Instead of merely generating a pulse at the
phase comparison point (as in other phase locked loop designs), it
generates signals that indicate whether the phase comparison has
occurred or is yet to occur.  It produces signal Retard for the first
half of the count period, and signal Advance for the second half, as
shown in Fig. 2.  These signals are used to advance or retard the
frequency generation counters.

The specifications for Advance and Retard are shown in Table 1.
  Table 1. Specifications for Advance and Retard
  Reference Frequency   Counts for 8 KHz Phase   Retard   Advance
                        Comparison Frequency
  1.536 MHz             192 (0-191)              1-95      96-191
  1.544 MHz             193 (0-192)              1-95      96-192
  2.048 MHz             256 (0-255)              1-127    128-254

      The other key element in this invention is the phase-locked
loop, or ring.  A usual phase-locked loop would consist of a
reference
clock counter and a ring.  In this invention, the rings share one
reference clock counter, and the update signal (phase-locking) is
generated in a slightly different manner.  Fig. 3 shows the truth
table
diagram for a typical ring.  In this case, the ring performs a
division
by sixteen.

      Several rings are used in the implementation described here.
Some are relatively simple, like the sample ring shown Fig. 3.
Others
are more complex, because of the requirement to be able to generate a
constant output frequency, regardless of which of two values the
input
frequency has assumed.  Table 2 shows lists the function provided by
each r...