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Browse Prior Art Database

Method for Supporting Different Clocking Modes of Power Personal Computer 60X CPU Bus

IP.com Disclosure Number: IPCOM000116357D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 87K

Publishing Venue

IBM

Related People

Amini, I: AUTHOR [+6]

Abstract

The PowerPC* 60x bus architecture defines several modes of clocking for CPU bus in a PowerPC based system. The different modes of clocking refer to the internal frequency of the CPU versus the external frequency of the CPU bus. These different modes can be grouped into two categories: Single clocking and multiple clocking. In Single clocking mode, both internal CPU logic and the external CPU bus operate at the same frequency. In multiple clocking mode, as the name suggests, the internal CPU logic operates at a frequency which is an integer multiple of the external CPU bus frequency, e.g., 2:1, 3:1. The CPU bus timings are different for the single clocking mode.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method for Supporting Different Clocking Modes of Power Personal
Computer 60X CPU Bus

      The PowerPC* 60x bus architecture defines several modes of
clocking for CPU bus in a PowerPC based system.  The different modes
of clocking refer to the internal frequency of the CPU versus the
external frequency of the CPU bus.  These different modes can be
grouped into two categories: Single clocking and multiple clocking.
In Single clocking mode, both internal CPU logic and the external CPU
bus operate at the same frequency.  In multiple clocking mode, as the
name suggests, the internal CPU logic operates at a frequency which
is an integer multiple of the external CPU bus frequency, e.g., 2:1,
3:1.  The CPU bus timings are different for the single clocking mode.
The operational differences in single clocking challenges the system
designer to either design a system which can only operate in one of
these modes or the designer needs to hinder the system performance in
order to support both modes.  This invention proposes a solution
which eliminates the need for two different implementation by
supporting both modes in one system.  Further, this solution does not
compromise optimum performance to accomplish this objective.

      Disclosed is a mechanism that allows the PowerPC 60x bus
interface logic to run in 1:1 or n:1 clocking modes.  This is
accomplished by utilizing a programmable register which defines the
mode of the bus.  When a different mode of operation is required,
programming this register will cause the bus interface logic to
switch between single or multiple clocking modes.  This register
defaults to a 1:1 clock mode upon power up.  It is important for the
bus to operate in the 1:1 clocking mode for ease of debug when
engineering tests are performed on a system intended to function in
multiple clocking mode.  The Power On Self Test (POST) code can then
set up the system in the correct mode by programming the bus clocking
mode register.

      When the memory controller is reset, e.g., power on reset,...