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Leadframe based, overmolded QFN style semiconductor package with preapplied solder depot, and methods of manufacturing the same.

IP.com Disclosure Number: IPCOM000116368D
Publication Date: 2005-Mar-30
Document File: 6 page(s) / 92K

Publishing Venue

The IP.com Prior Art Database

Related People

Robert Bauer: AUTHOR

Abstract

Overmolded, leadframe based QFN style semiconductor packages designs such as QFN, PQFN, ArrayQFN with or w/o exposed pads are aiming towards fine pitch lead layout structures. Simultaneously, the corresponding PCB footprint structures need to shrink in the same degree. In the course of this development, rework of PCB assembled devices becomes more difficult due to the high demand for accuracy of solder paste application, control of solder paste volume and package placement. Standard rework procedures as known today usually do not meet these requirements. This document describes a cost competitive and reliable way of establishing a rework process for QFN style semiconductor packages (QFN, PQFN, ArrayQFN w or w/o exposed pads) by using packages with pre-applied solder depots, and methods to manufacture the same.

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Page 1 of 6

Leadframe based, overmolded QFN style semiconductor package with preapplied solder depot, and methods of manufacturing the same.

Robert Bauer

© 2005 Freescale Semiconductor, Inc.

Page 2 of 6

Abstract

Overmolded, leadframe based QFN style semiconductor packages designs such as QFN, PQFN, ArrayQFN with or w/o exposed pads are aiming towards fine pitch lead layout structures. Simultaneously, the corresponding PCB footprint structures need to shrink in the same degree.

In the course of this development, rework of PCB assembled devices becomes more difficult due to the high demand for accuracy of solder paste application, control of solder paste volume and package placement. Standard rework procedures as known today usually do not meet these requirements.

This document describes a cost competitive and reliable way of establishing a rework process for QFN style semiconductor packages (QFN, PQFN, ArrayQFN w or w/o exposed pads) by using packages with pre-applied solder depots, and methods to manufacture the same.

© 2005 Freescale Semiconductor, Inc.

Page 3 of 6

Body

Semiconductors in QFN style packages such as standard QFN, PQFN, ArrayQFN with or w/o exposed pads have been successfully introduced into various high end applications in the automotive electronics sector as well as in the field of industrial electronics. In the course of the technical development, these package types are heading more and more towards fine pitch technology, simultaneously forcing the corresponding PCB footprint structures to shrink in the same degree. Reliable rework of assembled devices thereby becomes also more complex and harder to achieve.

The traditional method of reworking assembled semiconductor packages is carried out by heating up the device, removing the part from the PCB, cleaning the PCB footprint, dispensing solder paste on the footprint, placement of a new device and final reflow. For fine pitch QFN style packages the difficulties are related to the dispensing of an appropriate amount of solder paste in the right place on the fine PCB structures. Especially the PCB pads for the package I/O leads are a real challenge in this process. Dispensing paste on the very small PCB pad requires sophisticated & complex technical solutions (i.e. jet-valves) and can't be done with the typically applied, low cost dispensing devices. Other methods such as rework by solder paste printing using micro stencils do often drop out due to the high density packaging of the application boards.

This document introduces a cost competitive and reliable way of establishing a rework process for QFN style semiconductor packages (QFN, PQFN, ArrayQFN w or w/o exposed pads).

The basic idea promoted in this document is to provide QFN style packages with a pre- applied solder depot on I/O pads. The volume of the solder depot should be equal the amount of solder paste printed onto the recommended PCB package footprint in the

© 2005 Freescale Semiconductor, Inc.

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