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Programmable Snooping (Flush/Clean) Mechanism for Memory Controller I/O Subsystem Bridge in PowerPC Based System

IP.com Disclosure Number: IPCOM000116375D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Amini, I: AUTHOR [+6]

Abstract

The disclosure involves the use of a programmable snoop bit inside a memory controller to support Flush and Clean types of snoop transactions. When a snoop hit is to a dirty line on an I/O subsystem to system memory read cycle, the CPU could either perform a writeback and keep its cache line valid (Clean) or perform a writeback and invalidate its cache line (Flush), depending on the value of this bit. In turn, a PowerPC* system snooping protocol can be programmed to meet the system performance needed for a server or client system.

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Programmable Snooping (Flush/Clean) Mechanism for Memory Controller
I/O Subsystem Bridge in PowerPC Based System

      The disclosure involves the use of a programmable snoop bit
inside a memory controller to support Flush and Clean types of snoop
transactions.  When a snoop hit is to a dirty line on an I/O
subsystem to system memory read cycle, the CPU could either perform a
writeback and keep its cache line valid (Clean) or perform a
writeback and invalidate its cache line (Flush), depending on the
value of this bit.  In turn, a PowerPC* system snooping protocol can
be programmed to meet the system performance needed for a server or
client system.

      On any I/O subsystem write cycles to system memory, the memory
controller will snoop the L1/L2 caches for valid data.  If the snoop
hit is to a dirty L1/L2 cache line, then the CPU performs a writeback
and invalidates its cache line, regardless of the programmable snoop
bit value (Clean or Flush), because the I/O Subsystem will overwrite
the cache line data in system memory.  A Memory controller always
performs a Flush snoop cycle on all write cycles.  When an I/O
Subsystem performs read cycles from system memory, there is a
performance gain when programming this bit as Clean snoop type for
client systems or Flush snoop type for server systems.

        When this bit is a Clean snoop type, the memory controller
will snoop for every I/O subsystem read cycle if the L1/L2 caches are
of a store-in type.  On a snoop hit to a dirty cache line, the CPU
will perform a writeback and  keep its cache line valid for the next
CPU access.  This will reduce the number of accesses between the CPU
and system memory.  But, it will disable the function of "conditional
snooping" because the memory controller needs to snoop all the time
to maintain  data integrity of the system memory on any I/O read
cycles.

      When th...