Browse Prior Art Database

System Using Dual Output Smart First In/First Out to Allow Concurrent Writing to Memory and Input/Output Devices in a Personal Computer System

IP.com Disclosure Number: IPCOM000116383D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 129K

Publishing Venue

IBM

Related People

Amini, I: AUTHOR [+6]

Abstract

Disclosed is a mechanism which may be used in personal computer systems to improve system performance and throughput. In a typical system CPU accesses are performed in a serial fashion. This invention uses parallelism to improve performance. The parallelism is accomplished using a dual output First In/First Out (FIFO) design which accommodates parallel access to both memory and PCI devices when both types of transactions have been posted in the FIFO.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 47% of the total text.

System Using Dual Output Smart First In/First Out to Allow Concurrent
Writing to Memory and Input/Output Devices in a Personal Computer
System

      Disclosed is a mechanism which may be used in personal computer
systems to improve system performance and throughput.  In a typical
system CPU accesses are performed in a serial fashion.  This
invention uses parallelism to improve performance.  The parallelism
is accomplished using a dual output First In/First Out (FIFO) design
which accommodates parallel access to both memory and PCI devices
when both types of transactions have been posted in the FIFO.

      The memory controller consists of three major interfaces with
three modules each responsible for transferring data on that
interface.  These three interface PowerPC CPU interface, memory
interface and PCI interface, are connected electrically using
dedicated signals and buses internal to the memory controller.  The
CPU interface consists of a dual output FIFO which directs CPU
transactions to the other interfaces.  Two sets of signals are used
for transferring data fro the CPU interface FIFO to memory and PCI
interfaces.  The data transfer signals the memory interface are:
  o  MEM_TS#  - Signals the start of a memory transfer
  o  MEM_RDY# - Signals the completion of the transfer
  o  MEM_ADDR - Memory address
  o  MEM_DATA - Memory write data

The data transfer signals for the PCI interface are:
  o  PCI_TS#  - Signals the start of a PCI transfer
  o  PCI_RDY# - Signals the completion of the transfer
  o  PCI_ADDR - PCI address
  o  PCI_DATA - PCI write data

      The dual output FIFO can be implemented in many ways, however,
in this disclo the implementation of the FIFO is of no concern.  A
simple implementation is shown in the Figure.  In this example the
FIFO consists of two banks.  CPU write data is steered into either a
memory FIFO bank or a PCI FIFO bank.  An address decoder is utilized
to determine whether the transaction is a memory tra a PCI transfer
so that it is steered to the corresponding FIFO bank.

      To help describe the disclosure consider this sequence of
transactions and the corresponding number of bus cycles to complete
each one:
  1.  Memory Write transaction (A-requires 10 cycles to complete)
  2.  PCI Write transaction (B-requires 20 cycles to complete)
  3.  PCI Write transaction (C-requires 7 cycles to complete)
  4.  Memory Write transaction (D-requires 5 cycles to complete)
  5.  Memory Write transaction (E-requires 10 cycles to complete)

      In a typical system utilizing a FIFO without the dual output
parallel transaction processing the above sequence of transactions
completes in a total of 52 cycles.  However, when using the dual
output FIFO as described in this invention, transaction B starts
shortly after transaction A say within 2 clocks.  Transaction B is a
slow transaction so while that transaction is in progress transaction
A is complete...