Browse Prior Art Database

System for Detection of and Recovery from Invalid Central Processing Unit Bus Transaction

IP.com Disclosure Number: IPCOM000116399D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Amini, I: AUTHOR [+6]

Abstract

The Central Processing Unit (CPU) interfaces to memory and I/O subsystems using a specific protocol. This protocol defines a set of transactions that can be requested by the CPU. Typically, a given system only supports a subset of the bus protocol. In these systems, the CPU may erroneously operate in the unsupported protocol. When unsupported transactions are requested, the system is unable to handle the transaction. This, in turn, typically causes the system to hang.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

System for Detection of and Recovery from Invalid Central Processing
Unit Bus Transaction

      The Central Processing Unit (CPU) interfaces to memory and I/O
subsystems using a specific protocol.  This protocol defines a set of
transactions that can be requested by the CPU.  Typically, a given
system only supports a subset of the bus protocol.  In these systems,
the CPU may erroneously operate in the unsupported protocol.  When
unsupported transactions are requested, the system is unable to
handle
the transaction.  This, in turn, typically causes the system to hang.

      This disclosure describes a system to detect unsupported and
invalid transactions that will lead to an effective recovery from a
potential hang condition.  While the concepts in this disclosure are
generally applicable to any standard microcomputer bus, this
disclosure
uses the PowerPC* 60X microprocessor bus to illustrate these
concepts.

      The memory controller interfaces to the CPU by communicating
over a CPU bus.  The memory controller consists of a CPU bus
interface module to control CPU communications and other modules.
This invention is utilized in the memory controller CPU interface
module which consists of transaction decode unit, transaction
processing unit and transaction error unit.  Transaction decode unit
interprets the control signals on the bus to determine the type of
transaction that is requested by the CPU.  Transaction processing
unit in the CPU interface module executes the transaction requested
using decoded signals from the transaction decoding unit to control
its state machines.

      When an invalid transaction is detected by the transaction
decoding unit, a special signal is asserted signalling the
transaction processing unit that the current transaction is invalid
and should not be processed.  The same signal is used to alert the
transaction error unit in the CPU interface module that an invalid
t...