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Method to Transition a Memory Controller into Lower Power Mode Allowing the Main Clock to be Shut Off While Memory Refresh Operation is Maintained

IP.com Disclosure Number: IPCOM000116411D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Amini, I: AUTHOR [+6]

Abstract

Disclosed is a Low-Power mode transition scheme for a memory controller in a PowerPC* based system which would allow the main system clock (1) to be shut of when a system enters into a suspended state. The transition should allow for memory to be refreshed in both the Normal and Low-Power states without any interruptions.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 85% of the total text.

Method to Transition a Memory Controller into Lower Power Mode Allowing
the Main Clock to be Shut Off While Memory Refresh Operation is Maintained

Disclosed is a Low-Power mode transition scheme for a memory
controller in a PowerPC* based system which would allow the main
system clock (1) to be shut of when a system enters into a suspended
state.  The transition should allow for memory to be refreshed in
both the Normal and Low-Power states without any interruptions.

      The system uses the SUSP_STATE# signal (2) to indicate the
transition of entering/exiting the Low-Power state.  During Low-Power
state, the main clock is shut down and the refresh cycles are
generated
from the real time clock (3).  The real time clock is a low frequency
clock (32 Khz) that is typically used in the personal computers.

      The memory controller enters the low-power mode as the
SUSP_STATE# signal is act Its arbiter (4) boardcast the LPWR_MODE#
(5).  The normal refresh logic (6) request the memory bus to do a
refresh cycle if there is no refresh cycle already in progress.  The
arbiter grants the bus to allowed it to perform the refresh cycle.
Once the refresh is done, the arbiter informs the refresh logic to
switch to the low-power refresh logic (7).  The main clock is shut
down and the memory control generates low-power refresh cycles on
every subsequent transition of the real time clock.

      When the system is ready to return to the normal mode of
operation, it will...