Browse Prior Art Database

Method for "Smart Prefetch" of Data from Main Memory by a Memory Controller for Access by a CPU

IP.com Disclosure Number: IPCOM000116413D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Amini, I: AUTHOR [+6]

Abstract

Disclosed is an efficient method for predicting when to prefetch data from the main memory for access by a PowerPC* processor. "Smart Prefetching" is utilized to provide greater performance in the memory subsystem, thereby, increasing the overall system performance and throughput.

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Method for "Smart Prefetch" of Data from Main Memory by a Memory
Controller for Access by a CPU

      Disclosed is an efficient method for predicting when to
prefetch data from the main memory for access by a PowerPC*
processor.  "Smart Prefetching" is utilized to provide greater
performance in the memory subsystem, thereby, increasing the overall
system performance and throughput.

      A common prefetching technique used in personal computers is
blind prefetching.  "Blind prefetching" refers to the technique where
a memory controller prefetches data on every memory access.  Blind
prefetching can improve the overall memory subsystem performance,
however, the hit rate for prefetched data is typically low.  A low
hit rate means that many prefetch operations must be cancelled in
order to start fetching the needed data.  There is a penalty involved
in cancelling a prefetch operation which reduces the performance
gains from blind prefetching.

      This disclosure proposes a method for more accurately
predicting the next memory access address.  Therefore, a smart
prefetching technique can be utilized to access data resulting in a
higher hit rate which increases the system performance.  Smart
prefetching applies the principles of "locality of reference" in
computer programs in combination with the use of TC, TSIZE, TBST and
TT(1) signals to predict the address of the next instruction to be
accessed by the PowerPC CPU.

      Smart prefetching begins with the first cache line read access
to Instruction memory (Code read).  The PowerPC CPU reque...