Browse Prior Art Database

Optimal Dispatch Algorithm for Similar Functional Units

IP.com Disclosure Number: IPCOM000116416D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Golla, RT: AUTHOR [+2]

Abstract

This disclosure describes an algorithm for dispatching instructions optimally between two similar functional units. Functional units may be considered similar if the instruction set executed by one functional unit is a proper subset of the instruction set executed by the other functional unit.

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Optimal Dispatch Algorithm for Similar Functional Units

      This disclosure describes an algorithm for dispatching
instructions optimally between two similar functional units.
Functional units may be considered similar if the instruction set
executed by one functional unit is a proper subset of the instruction
set executed by the other functional unit.

      A processor consisting of an Instruction Issue Unit (IIU), a
Simple Fixed-point unit (SFX) and a Normal Fixed-point unit (FXU)
will be considered.  The instructions executed by each of the
fixed-point units are defined below:
  instruction set A = {cmp, add}
  instruction set B = {multiply, divide}
  instructions executed by SFX = set A = {cmp, add}
  instructions executed by FXU = set A Union set
   B = {cmp,add, multiply, div}

      The IIU can dispatch up to two instructions per cycle.
Dispatch to the SFX and FXU is regulated by whether each of the units
is busy or not.  A fixed-point unit will become busy if it is unable
to immediately begin execution of the instruction it is dispatched
(e.g., the source operands of the instruction are not available yet).
A fixed-point unit will also become busy if the instruction it is
working on requires multiple cycles to finish execution (e.g., a
multiply instruction).  Each fixed-point unit can only execute one
instruction at time.  If a unit is busy, instructions cannot be
dispatched to the given unit that cycle.  Two instructions (i0 and
i1) are eligible for dispatch by the IIU every cycle.  These
instructions are dispatched in order.  Instruction i1 cannot be
dispatched unless instruction i0 is dispatched first.

      The optimal dispatch algorithm for such a processor can be
obtained by considering the fact that all of the instructions
executed by the SFX can be executed by the FXU but not vice versa.
One can consider the case where i0 is a  cmp instruction, i1 is a
multiply instruction and neither fixed-p...