Browse Prior Art Database

Increased Chip Wireability through More Efficient Power Distribution

IP.com Disclosure Number: IPCOM000116425D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 102K

Publishing Venue

IBM

Related People

Greenwood, VP: AUTHOR [+2]

Abstract

Disclosed is a solution to the problem of inefficient chip power grids.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 40% of the total text.

Increased Chip Wireability through More Efficient Power Distribution

      Disclosed is a solution to the problem of inefficient chip
power grids.

      Traditional chip power distribution has been accomplished
through an extensive and wasteful "grid" method.  This has not been a
problem in the past but as our chip technology gets denser,
transistors become closer and closer, forcing us to put more wires in
less area.  Quite simply, if the amount of chip metal that is used
for things such as a power grid can be reduced, that metal for
circuit wiring can be used.

This solution creates a more efficient power distribution structure.
In the past, the traditional power "grid" looked like the following:
        gnd  vdd  gnd  vdd  gnd  vdd  gnd  vdd
         |    |    |    |    |    |    |    |
  gnd----*----|----*----|----*----|----*----|----
         |    |    |    |    |    |    |    |
  vdd----|----*----|----*----|----*----|----*----
         |    |    |    |    |    |    |    |
  gnd----*----|----*----|----*----|----*----|----
         |    |    |    |    |    |    |    |     * = upper to
  vdd----|----*----|----*----|----*----|----*----     lower metal
         |    |    |    |    |    |    |    |         connection
  gnd----*----|----*----|----*----|----*----|----
         |    |    |    |    |    |    |    |
  vdd----|----*----|----*----|----*----|----*----  gnd=ground
         |    |    |    |    |    |    |    |
  Fig. 1:  Traditional horizontal/vertical power grid.

      This grid pattern is traditionally repeated for every pair of
metal layers from the top of the chip to the bottom with something on
the order of 20% of each metal layer being used for this sort of
power distribution.  The goal was simply to create something simple
that provided good distribution.

      With a need for more metal for circuit wiring purposes and a
need for fatter wires across very large chips, we must be more
efficient with such metal consuming structures.  The following as a
solution is proposed:

      First, wire all the lower level circuits to vdd and gnd using
power "rails".  This is already commonly done and is illustrated
below:
      gnd  vdd  vdd  gnd        gnd  vdd  vdd  gnd
      |    |    |    |          |    |    |    |      / = ckt
boundary
  ////|////|/  /|////|////  ////|////|/  /|////|////  | = metal
  /   |    |/  /|    |   /  /   |    |/  /|    |   /
  ////|////|/  /|    |   /  /   |    |/  /|    |   /
  ////|////|/  /|    |   /  ////|////|/  /|    |   /
  /   |    |/  /|    |   /  ////|////|/  /|////|////
  /   |    |/  /|////|////  ...