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Write Frequency Reduction into the Liquid Crystal Display Source-Drivers with Three Memory Banks

IP.com Disclosure Number: IPCOM000116434D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Nishi, S: AUTHOR [+3]

Abstract

The structure of this method has three memory banks and two data multiplexers. Video data is written to each memory bank in sequence by a frequency, then read simultaneously from two of the memory banks by half frequency. Read data from three memory banks multiplex two data bus. One data bus connects with the odd Liquid

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 76% of the total text.

Write Frequency Reduction into the Liquid Crystal Display Source-Drivers
with Three Memory Banks

      The structure of this method has three memory banks and two
data multiplexers.  Video data is written to each memory bank in
sequence by a frequency, then read simultaneously from two of the
memory banks by half frequency.  Read data from three memory banks
multiplex two data bus.  One data bus connects with the odd Liquid

Crystal Display (LCD) source-drivers; the other connects with the
even drivers.

      Fig. 1 shows this disclosure's block.  Fig. 2 shows it's timing
chart.  Procedure is the following, and is repeated cycle from T1 to
T12 by each line.  (The each LCD source-driver is named as "X1"
-"X10".  "D01"-"D10" are data which is written into the each LCD
source-driver.  The write frequency name is "S".  "B1" is data bus
name to connect with the odd LCD source-driver.  "B2" is data bus
name to connect with the even LCD source-driver.  "M1"-"M3" are
memory banks which have one LCD source-driver's memory capacitance.
"P1" is data multiplexer on the side "B1".  "P2" is  on the side
"B2".)  During "T1" cycle, "D01" is written into "M1" with "S".  For
"M2" and "M3", do not write or read.  During "T2" cycle, the first
half "D01" is read from "M1" with "S"/2, flow via "B1" by "P1" and is
written into "X1".  "D02" is written into "M2" with "S".  For "M3",
do not write or read.  During "T3" cycle, the latter half "D01" is
read from "M1" with "S"/...