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Method for Maintaining Coherency When Entering and Exiting Low-Power Mode in a Memory Controller Supporting Transaction Posting

IP.com Disclosure Number: IPCOM000116442D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 139K

Publishing Venue

IBM

Related People

Amini, I: AUTHOR [+6]

Abstract

When entering and then exiting low-power mode in a system that utilizes a memory controller with on chip buffering, the system must carefully stage the low-power mode entry and exit to guarantee that the posted transactions in the on-chip buffers can be completed when low-power mode is exited. To accomplish this, the system must be restored to the same state it was in when entry into low-power mode first happened. If the system is not restored to the same state, the completion of the posted transactions will cause a coherency problem because the system has no way to determine what transactions had previously been posted to the on-chip buffers.

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Method for Maintaining Coherency When Entering and Exiting Low-Power
Mode in a Memory Controller Supporting Transaction Posting

      When entering and then exiting low-power mode in a system that
utilizes a memory controller with on chip buffering, the system must
carefully stage the low-power mode entry and exit to guarantee that
the posted transactions in the on-chip buffers can be completed when
low-power mode is exited.  To accomplish this, the system must be
restored to the same state it was in when entry into low-power mode
first happened.  If the system is not restored to the same state, the
completion of the posted transactions will cause a coherency problem
because the system has no way to determine what transactions had
previously been posted to the on-chip buffers.  If the posted
transactions are invalidated (effectively cancelled) by the memory
controller upon a system request to enter low-power mode, the
coherency problem still remains because the software has no way of
determining what transactions were invalidated.  This causes the
software and hardware to be out of sync.

      Disclosed is an arbitration mechanism to delay entry into
low-power mode until all on-chip buffers are flushed, that is all
posted transactions are completed.  Once the buffered transactions
are completed, the contents of memory are retained using a low-power
refresh technique.  Upon exiting from low-power mode, two scenarios
are possible.  If the system is restored to the same state as when
low-power mode was entered, then the system operation may continue
normally.  If the system was restored to a different but known state,
e.g., CPU was reset, then the memory contents are in a coherent state
because the transactions were completed before entering low-power
mode and the software is in sync with the hardware.  The operation
can continue normally.  Because the coherency is maintained no
special software techniques are required to ensure system integrity.

      Referring to the Figure, the memory controller consists of five
functional blocks: Arbitration logic, CPU interface logic, PCI
interface logic, Memory interface logic and Refresh logic.  The
arbitration logic controls access to memory bus by CPU, PCI and
refresh agents.  It also controls entry into and exit from the
low-power mode.  The CPU interface logic and PCI interface logic
provide the intelligence for interfacing to the CPU and PCI buses.  A
FIFO in each module is used to post transaction for improved
performance.  The memory interface logic interfaces to memory on
behalf of CPU, PCI and refresh agents.  Finally, refresh logic
contains timers and controls to process refresh operations for the
random access memory (RAM).

      During normal operation the arbiter arbitrates between CPU and
PCI agents to determine which agent will own the memory bus.  The
CPU_REQ# and PCI_REQ# signals are asserted by the CPU and PCI agents
respectively to request a memory b...