Browse Prior Art Database

GPP Bus Driving

IP.com Disclosure Number: IPCOM000116445D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 52K

Publishing Venue

IBM

Related People

Baudrion, PY: AUTHOR [+2]

Abstract

Disclosed is a method to optimize the loading of the bus to improve the speed transfer between the DATA bank, CODE bank and microprocessor. It was necessary for this circuitry also to improve the exchange speed during transfer at the better performance as DMA between I/Os and SRAM. This approach is able without aditional circuitry to supervise the data transfer With multiple processors.

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GPP Bus Driving

      Disclosed is a method to optimize the loading of the bus to
improve the speed transfer between the DATA bank, CODE bank and
microprocessor.  It was necessary for this circuitry also to improve
the exchange speed during transfer at the better performance as DMA
between I/Os and SRAM.  This approach is able without aditional
circuitry to supervise the data transfer With multiple processors.

      The prior of the art is to use bidirectional drivers, but a
loading problem appeared in the case of multiple I/Os due to
capacitive loading on each drivers.  This problem is solved by added
wait states on the microprocessor.  This approach lowers the
performances (Fig. 1.).  SOLVED - The proposal is to use a
cross-point switch and distribute the capacitive loading on the three
sides evenly (Fig 2).

Thus, the following resulted:
  o  A point to point link between SRAM and micro-processor with zero
      wait states.
  o  A point to point link between  the DMA function on the SRAM and
      the I/Os circuitry with zero wait states.
  o  Less loading on the DATA bus which allowed better adjusted
      performances.
  o  For other functions, the poor performances were adjusted with
      each I/O depending on the interface performances needed.