Browse Prior Art Database

Endian Switching Mechanism for a Memory Controller/Input/Output Subsystem in a Power Personal Computer Based System

IP.com Disclosure Number: IPCOM000116448D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 127K

Publishing Venue

IBM

Related People

Amini, I: AUTHOR [+6]

Abstract

Disclosed is an efficient Endian switching mechanism for a memory controller PowerPC* system. This mechanism insures that data integrity is upheld in case of that the memory controller / I/O subsystem bridge comes up in the correct "endian" mode in case of power-on reset as well as when it exits the suspend mode or low power mode.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Endian Switching Mechanism for a Memory Controller/Input/Output Subsystem
in a Power Personal Computer Based System

      Disclosed is an efficient Endian switching mechanism for a
memory controller PowerPC* system.  This mechanism insures that data
integrity is upheld in case of that the memory controller / I/O
subsystem bridge comes up in the correct "endian" mode in case of
power-on reset as well as when it exits the suspend mode or low power
mode.

      There are two modes (Big Endian and Little Endian) that
represent the method for storing data types that are larger than one
byte.  The Big Endian mode device highest-order byte in the lowest
address and the Little Endian device stores the in the lowest
address.  The memory data flow for PowerPC based systems is being
designed to use the Bi-Endian memory architecture.  This means that
main memory will support both Endian modes and also run in the same
endian mode as the CPU (PowerPC).  This requires the memory
controller/ I/O subsystem bridge to handle the data and address
translations between the CPU and memory buses and also between the
CPU and I/O buses.  The default mode of operation for the CP is Big

Endian.  The endianness of the planar is changed via port 92 in
accordance Reference Platform Architecture Specification.  In order
to change the endian mode of the planar from big endian to little
endian, the CPU is required to write  a '1' to bit 1 (the second
least significant bit) PCI I/O register at Port 92.  To change the
endian mode of the planar from little endian the CPU is required to
write a '0' to bit 1 of the port 92 register.  The memory controller
/ I/O subsystem bridge initiates all I/O bus cycles on behalf of the
CPU when it accesses the I/O bus.  The I/O device (which has the Po
drives a signal N_LITTLE_BIG (0 = Big Endian, 1 = Little Endian) to
the memory c which tells it what endian mode the CPU is in.

      This invention solves the following potential PowerPC system
problem: The software requests a change of endian mode.  The CPU
(PowerPC) requests the I/O subsystem bridge to initiate a PCI write
cycle to PCI I/O port 92 on its behalf.  The memory controller / I/O
subsystem bridge starts the PCI transaction to port 92 by asserting
N_FRAME (address phase) and eventually N_IRDY (initiator ready
indicates that the write data is valid on The PCI I/O device switches
the N_LITTLE_BIG signal before the write cycle is actually completed
(the PCI I/O device keeps N_TRDY deasserted inserting wait states in
the data phase).  The N_L the memory controller / I/O subsystem
bridge to handle data and address translat between the CPU and PCI
buses.  The switching of the N_LITTLE_BIG signal results I/O
subsystem bridge changing its endian mode prematurely and swapping
its data The incorrect data gets driven onto the PCI AD lines and
eventually written (whe N_TRDY) to the port 92 register resulting in
no 'endian' change of the pla...