Browse Prior Art Database

Load of Writable Control Store

IP.com Disclosure Number: IPCOM000116452D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 137K

Publishing Venue

IBM

Related People

Kruse, RE: AUTHOR [+3]

Abstract

Disclosed is a mechanism that enables a Writeable Control Store (WCS) to be loaded at processor speed (rather than at service processor speed) with a minimum of additional hardware. This solution allows the execution element which is controlled by Licensed Internal Code (LIC) (also known as microcode) to perform the following tasks: set up the hardware load controls, initiate the load sequence, perform the actual writing of the control store, then return control to LIC to resume normal operations. This can be done largely using controls that already exist within most LIC-controlled processor designs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 39% of the total text.

Load of Writable Control Store

      Disclosed is a mechanism that enables a Writeable Control Store
(WCS) to be loaded at processor speed (rather than at service
processor speed) with a minimum of additional hardware.  This
solution allows the execution element which is controlled by Licensed
Internal Code (LIC) (also known as microcode) to perform the
following tasks:  set up the hardware load controls, initiate the
load sequence, perform the actual writing of the control store, then
return control to LIC to resume normal operations.  This can be done
largely using controls that already exist within most LIC-controlled
processor designs.

      The solution described here is based on a generic
LIC-controlled Execution Element (EE).  It utilizes controls
originally designed for loading a WCS via a direct connection to a
service processor, and provides a hardware + LIC mechanism for
getting new WCS data to those controls at a rate commensurate with
the machine cycle time.  An additional feature of this mechanism is
that it allows the WCS load to take place in all processors in a
system simultaneously.  On some systems, this yields an improvement
of several orders of magnitude in the time that processors are
unavailable during a load of WCS on all processors (a reduction in
time from seconds to milliseconds).

      The WCS load operation is performed by setting up a data
pipeline in which bytes of WCS data are fetched into operand buffers,
gated to dataflow registers, passed to the WCS load controls, and
written to the WCS arrays.  This operation is initiated by LIC, but
proceeds under complete hardware control (since LIC must be read from
the WCS, which is being re-written during the load, new LIC words
cannot be executed during the load itself).  During the load, the
operand fetch controls are fetching the new WCS data, much as they
would fetch a long operand during instruction execution; the WCS load
controls are receiving data from the rest of the EE and writing it
into the WCS arrays, and the rest of the EE is executing a fixed word
of LIC, specified by the LIC at the start of the load.  In this way,
LIC retains much of the control over what will happen during the WCS
load, allowing for greater flexibility and simpler testing of the
load function.

      Use of this mechanism requires new processor LIC, in the form
of a new micro-assist.  Support is also required from the service
processor (the external machine which controls and assists the main
processor) which must format the new WCS data in storage and initiate
the WCS load assist on each processor.

The WCS load state machine to implement this disclosure is described
below:
  o  State: WCS Load Controls Function.
  o  Idle: No load operation in progress.  If a partial WCS load is
      supported, the controls will accept address and length values
      using the WCS load data path and special micro-orders.  The
state
      machine remai...