Browse Prior Art Database

Pel Clock Synchronization for Reduced Scan-to-Scan Jitter in a Laser Printer

IP.com Disclosure Number: IPCOM000116464D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 104K

Publishing Venue

IBM

Related People

Hoskins, PK: AUTHOR [+2]

Abstract

A method of synchronizing a digital clock to an an asynchronous signal.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Pel Clock Synchronization for Reduced Scan-to-Scan Jitter in a Laser
Printer

      A method of synchronizing a digital clock to an an asynchronous
signal.

      Specifically, in a laser printer, a pel clock must be
synchronized to a laser position signal as the laser scans past a
sensor.  In this disclosure, the phase of the pel clock is adjusted
to a beam detection signal.

      This circuit selects one of an even number of clock phases
which can be created with a precision multiple tap digital delay
module.  The entire selection circuit can be contained in a single
Programmable Logic Device (PLD).  This design is distinguished from a
previous multiple phase solution by its encoding circuit using a gray
code.  The code represents the one phase of the clock which is
closest to the leading edge of the beam detection signal.  This phase
is then selected and gated to the output of the PLD.  The output can
be held off while the clock is changing selected phases by another
input called end of drum.  The encoding allows the selection circuit
to fit in a single device.  The gray code is an important part of
this design to ensure that the accuracy of the synchronization.  The
final output from the PLD is a clock (pel clock) which is
synchronized to the input signal (beam detection).

      Fig. 1 shows the overall block diagram and the internal block
diagram of the PLD.  The drawing shows an eight phased circuit
although this method will work with any even number of phases.  As
the
number of phases is decreases, however, the accuracy also decreases.

      The eight clock phases are equally delayed from each other and
the delay from the first clock phase to the last does not exceed the
total clock period.  This spacing of the delays creates eight phases
which are then available to select from across a pel clock period
(Fig. 2).

      The latches in Fig. 1 are edge triggered with the beam detect
signal used as the clock to the latches.  The data to the latches is
the gray code created from the eight to three gray code encoder.
Since the oscillator is free running, the eight phases and the three
encoded lines are also constantly changing.  ...