Browse Prior Art Database

Cycle Steal at Rename Register

IP.com Disclosure Number: IPCOM000116468D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 92K

Publishing Venue

IBM

Related People

Pennington, A: AUTHOR [+2]

Abstract

Disclosed is a method of reducing clock cycle time in a superscalar microprocessor using register renaming through the use of "cycle stealing" (stealing time from the next clock cycle to complete work started in the previous cycle). A specific case is presented in order to illustrate the problem and solution. Since the problem and the solution are so tightly coupled to register renaming, the mechanism of register renaming is first discussed in order to properly expose the problem.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Cycle Steal at Rename Register

      Disclosed is a method of reducing clock cycle time in a
superscalar microprocessor using register renaming through the use of
"cycle stealing" (stealing time from the next clock cycle to complete
work started in the previous cycle).  A specific case is presented in
order to illustrate the problem and solution.  Since the problem and
the solution are so tightly coupled to register renaming, the
mechanism of register renaming is first discussed in order to
properly expose the problem.

      In a superscalar microprocessor where multiple instructions can
be dispatched to multiple pipelines, register renaming may be used to
solve the following three problems.
  1.  To resolve data dependencies such as the "write after write"
and
       the "write after read" dependencies, which increases the
chance
       of discovering parallelism in a sequential program.
  2.  To support "out of order" execution of instructions while
having
       the appearance of in-order completion, keeping the pipeline as
       busy as possible.
  3.  To provide a "recovery" mechanism to support "speculative
       execution" using some branch prediction technique.  The 604
       features two levels of branch prediction that enables it to
       continue to speculatively dispatching instructions without
       waiting for the completion of instructions preceding a branch
       that may have been incorrectly predicted.

      Register renaming solves these problems by allocating a new
register for every new value produced.  Each time a new register is
allocated, a destination tag is associated with this register so that
when the instructions arrives at the end of the execution pipeline,
it is able to update this newly allocated register.  Any subsequent
instructions that access the original register for reading will
instead get the value of the newly allocated copy of the register.
The antidependencies (also called "write after read") and the output
dependencies (also called "write after write") are removed, thus
increasing the chance for discovering parallelism in the program.
This allocation of copies of registers also allows "out of order"
execution, allowing shorter latency instructions to finish and update
its copy of a register, without waiting for a previous instruction to
finish.

      Since a register may be "renamed" multiple times, the "most
recently allocated" copy must somehow be marked so that subsequent
instru...