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Browse Prior Art Database

Parity Read-Ahead Buffer for Raid System

IP.com Disclosure Number: IPCOM000116514D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 114K

Publishing Venue

IBM

Related People

Munetoh, S: AUTHOR [+3]

Abstract

Disclosed is a parity cache used with the dual- or multiple-bus- architecture to speed up the write operation in the RAID 4 and RAID 5 systems, which use parity to improve the reliability of their stored data. The parity cache reads in the parity when the corresponding data are read, and speeds up the following write operation by using the parity and eliminating the access to a Hard Disk Drive (HDD). The parity cache also keeps a record of the parity calculated in the write operation, and speeds up the next write operation by reusing the parity.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Parity Read-Ahead Buffer for Raid System

      Disclosed  is  a parity  cache  used  with the  dual- or
multiple-bus- architecture to speed up the write operation  in the
RAID 4 and RAID 5 systems, which use  parity to improve the
reliability  of their stored data.   The parity cache  reads in  the
parity when  the corresponding data are  read, and speeds up  the
following write operation  by using the parity and eliminating the
access to a Hard Disk Drive (HDD).  The parity cache also keeps a
record of the parity calculated in the write operation, and speeds
up the next write operation  by reusing the parity.

      Fig. 1 shows an example of a dual-bus-architecture RAID system
using this invention.  This RAID system consists of a host InterFace
(IF) with the host system's I/O bus, as well as a data cache, a
multiplexer, a crossbar SWitch (SW), a Parity Generator (PGEN), a
parity cache, and HDDs.  The parity cache consists of a parity buffer
and parity tags.  The parity buffer keeps parity, while the parity
tags record the properties of the parity saved in the parity buffer.
The parity cache is controlled by a micro control unit or special
hardware in the RAID system.

      The parity buffer is divided into lines.   For each line, a
corresponding parity tag is made.  Fig. 2 shows the structure of a
set of parity tags.  Each tag consists of fields labeled "valid
flag", "offset", "len", "dirty flag", "LBA", and "AccessNo".  \Valid
flag" shows whether the content of the tag is valid.  "Offset" and
"len" show the initial offset and length of the valid parity in the
corresponding line.  "Dirty flag" shows whether the content of the
corresponding line is the same as the parity in the HDD or is updated
only in the line.  "LBA" shows the LBA of the parity cached in the
corresponding line.  "AccessNo" shows the number of accesses used for
the LRU cache management method.  This invention is applicable to
both write-through cache and write-back cache.  For write-through
cache, "dirty flag" is not used.

      The parity tags, parity lines, and HDDs are controlled as
follows.  At the time of initialization, each "valid flag" is set as
invalid.  When data are read, the following control method is used.
If the corresponding parity is cached, the corresponding tag's
"AccessNo" is updated to the newest number, and any younger values of
other tags' "AccessNo" are incremented by 1.  If the corresponding
parity is not cached or is partially cached, an invalid tag or the
oldest tag is first selected. ...