Browse Prior Art Database

First In/First Out Control for Sector Buffer Band Width Assignment

IP.com Disclosure Number: IPCOM000116525D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Murakami, M: AUTHOR [+2]

Abstract

Disclosed is a method for adjusting the assignment of the band width of the sector buffer which is used on Hard Disk Drive (HDD). Several blocks such as Host, Drive, Micro Code and Pico Code access the sector buffer to load or store a program or a data, and share its definite band width by the time multiplex access. Host and Drive have First In/First Out (FIFO) to load or store a data from or to the sector buffer to keep the sustained data transfer. This disclosure is to adjust the bandwidth assignment for each block by controlling the number of words to access Host FIFO. And its adjustment can be achieved by the micro code on HDD.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

First In/First Out Control for Sector Buffer Band Width Assignment

      Disclosed is a method for adjusting the assignment of the band
width of the sector buffer which is used on Hard Disk Drive (HDD).
Several blocks such as Host, Drive, Micro Code and Pico Code access
the sector buffer to load or store a program or a data, and share its
definite band width by the time multiplex access.  Host and Drive
have First In/First Out (FIFO) to load or store a data from or to the
sector buffer to keep the sustained data transfer.  This disclosure
is to adjust the bandwidth assignment for each block by controlling
the number of words to access Host FIFO.  And its adjustment can be
achieved by the micro code on HDD.

      Generally Dynamic Random Access Memory (DRAM) is used as the
sector buffer and accessed at Fast Page Mode to use its band width
effectively.  To access N words at Fast Page Mode, time of {(2N+3) x
T} is required.  Where T is the period of the system clock.  {(2N+3)
x T} is an equation under one application and it varies according to
the usage of DRAM.  But anyway, time increases in proportion to the
number of words accessed.

      Fig. 1 shows the number of words and the order of the sector
buffer access by each block.  Host accesses 10words, Micro Code does
1word, Drive does 5words and Pico Code does 6words.  These accesses
are repeated at this order.  In this example, the band widths of
Host, Micro Code, Drive and Pico Code are as follows;
  Host:  10word / 56Tsec
  Micro Code:  1word / 56Tsec
  Drive:  5word / 56Tsec
  Pico Code:  6word / 56Tsec
 ...