Browse Prior Art Database

Instruction RAM Paging in a Harvard Architecture Multi-Processor Digital Signal Processing System

IP.com Disclosure Number: IPCOM000116560D
Original Publication Date: 1995-Oct-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 114K

Publishing Venue

IBM

Related People

Andrews, LP: AUTHOR [+6]

Abstract

Disclosed is a paging circuit for a Harvard Architecture Digital Signal Processing System. IRAM paging is a method of increasing Instruction RAM size without increasing the DSP Chip Pin count. In a multi-processing system, a group of processors will be executing a variety of tasks. These tasks would reside in different IRAM pages. Control must be passed from task to task, and caution must be used so that the Operating System Services and IRAM Paging Mechanism can be accessed from any IRAM page. This mechanism should also prevent any unauthorized or accidental switching of the current IRAM page. The paging mechanism for DRAM is described in (2). Paging using Direct Memory Access (DMA) is described in (1).

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Instruction RAM Paging in a Harvard Architecture Multi-Processor
Digital Signal Processing System

      Disclosed is a paging circuit for a Harvard Architecture
Digital Signal Processing System.  IRAM paging is a method of
increasing Instruction RAM size without increasing the DSP Chip Pin
count.  In a multi-processing system, a group of processors will be
executing a variety of tasks.  These tasks would reside in different
IRAM pages.  Control must be passed from task to task, and caution
must be used so that the Operating System Services and IRAM Paging
Mechanism can be accessed from any IRAM page.  This mechanism should
also prevent any unauthorized or accidental switching of the current
IRAM page.  The paging mechanism for DRAM is described in (2).
Paging using Direct Memory Access (DMA) is described in (1).

      This mechanism has the following features:
  1.  Operating System Services resident in both IRAM pages.  The
       Operating System Services and Interrupt Handlers are present
       in all IRAM pages to allow for efficient dispatching of tasks
       and exit routines, by providing automatic IRAM paging, thus
       preventing unnecessary IRAM page switching.
  2.  Individual control for multiple processor systems.  Multiple
       processors are supported by allowing each its own IRAM Paging
       Decode.  This will allow each processor access to any page of
       IRAM without affecting the instruction fetching of another
       processor in the same system.
  3.  Auto closing "window decode" to prevent accidental IRAM
switches.
       In order to prevent accidental IRAM switches, an auto closing
       Window Decode must be written to by the instruction prior to
the
       write to the Page Decode.
  4.  Remote processor access to IRAM Paging Mechanism.  A remote
Host
       Processor can use the IRAM Paging Mechanism for accessing the
       systems IRAM.  This can be achieved by writing to the DRAM
Decode
       areas via a DMA or Cycle Steal Write function.
  5.  IRAM page select bit(s) give additional bits of IRAM address
with
       the same number of I/O pins on a DSP Chip.

      The IRAM Paging Mechanism will be controlled via DRAM memory
writes.  Two (2) fixed DRAM memory locations in DRAM for each
processor in the system will be used to select which IRAM page the
next instruction will be fetched from, for that processor.

      The IRAM page switch is achieved when a processor writes to its
Window Decode address.  This will "prep" a subsequent DRAM memory
write to the Page Decode address with the actual page select.

      Note that multiple processors are supported (Fig. 1).  Each
processor has it's own DRAM locations allowing it to access any IRAM
page independently from the other p...