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Browse Prior Art Database

Color Register Loading Method

IP.com Disclosure Number: IPCOM000116584D
Original Publication Date: 1995-Oct-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Miyatake, H: AUTHOR [+3]

Abstract

Disclosed is a method of loading color register and doing block or flash write mode in one cycle. Using data gate signals and one strobe signal enables DRAM to get write data, write mask data and color register data in one cycle. Note that conventional block write and flash write in dual port DRAMs require a dedicated cycle for color register loading operation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 62% of the total text.

Color Register Loading Method

      Disclosed is a method of loading color register and doing block
or flash write mode in one cycle.  Using data gate signals and one
strobe signal enables DRAM to get write data, write mask data and
color register data in one cycle.  Note that conventional block write
and flash write in dual port DRAMs require a dedicated cycle for
color register loading operation.

      Fig. 1 shows circuitry diagram used in this disclosure.
Control Signal Generator makes latch clocks and mode signals from
CLK, DSN, BWN and FWN.  Latch clocks are DGCLKN, DICLKN and CRLCLKN.
Mode signals are BLOCK and FLASH.  DG Latch latches DG and DI Latch
latches DI, respectively, when each latch clock goes low.  WMASK is a
buffered signal of MASKDT latched in DG Latch.  INDATA conveys write
data, color register and column mask data.  Color Register gets
INDATA as color register data for block and flash write mode when
CRLCLKN is high.  Write Data Selector & Buffer selects CRDATA for
write data (WDATA) in block and flash write mode.  Write Driver
drives Data Line (DL) according to WMASK and WDATA.  In flash write
mode Flash Write Driver writes data into all Bit Lines (BL) at once.
In block write mode Column Decoder generates BSW from column address
(Ax) and column mask (INDATA) to control Column Switch.

      Fig. 2 shows the signal timing chart.  The first part is for
block write mode.  CLK begins the cycle of block write mode raising
BLOCK sig...