Browse Prior Art Database

Error Protection for Memory Addressing

IP.com Disclosure Number: IPCOM000116649D
Original Publication Date: 1995-Oct-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 93K

Publishing Venue

IBM

Related People

Blaum, M: AUTHOR [+4]

Abstract

A general method for the detection of addressing errors is disclosed. In addition to error detection, the proposed method also provides for immediate identification of the faulty address lines.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Error Protection for Memory Addressing

      A general method for the detection of addressing errors is
disclosed.  In addition to error detection, the proposed method also
provides for immediate identification of the faulty address lines.

      Error-correcting codes are widely used as a means of detecting
and correcting erroneous data (1,2).  In many applications the data
are stored in a memory unit, such as Random-Access Memory (RAM),
Read-Only Memory (ROM), or variants thereof.  In such situations the
usual practice is to protect the data by appending parity-check bits
to each data-word stored in the memory unit (2).  When the data-word
is later fetched, the parity-check bits are regenerated and compared
with the check bits retrieved from the memory.  If a difference
occurs during the comparison, the data-word read from memory is
declared to be in error, and the combination of the check-bit
patterns is sometimes employed to correct the erroneous data bits.
However, if one or more of the address bits is in error all the check
bits will obviously coincide, and incorrect data will be tagged as
valid.  Thus, the conventional error-correction schemes provide no
protection against memory addressing errors.

      Consider the following situation: a Processing Unit (PU) is
required to read and/or write data to a Memory Unit (MU) for its
operation.  Let the memory unit contain 2*n data cells or words, each
word consisting of m bits.  In this case the PU will access the data
by means of an a ddress-bus A composed of n address lines and a
data-bus D composed of m data lines.

      To access the data the n address lines A are set by the PU so
as to specify the precise memory location of one of the 2*n
data-words to be fetched, and the data-word itself is transferred
from the memory by means of the data-bus D.  However, a fault in one
of the n address drivers in the PU, a short/open circuit affecting
the address lines, and other possible defects may cause one or more
of the address lines A to be in error.  In this case the memory
location indicated by the values of the address lines -- as seen at
the MU -- is wrong, and an incorrect data-word will be fetched from
the memory.

      In such a case, if the system is to be protected against memory
addressing errors, the error detection/correction mechanism must be
located in the PU.  This property of our scheme, namely the
assumption that the MU has no processing capability, makes it more
useful than the t...