Browse Prior Art Database

Multi-Stage Interconnection Network Topologies for Large Systems

IP.com Disclosure Number: IPCOM000116661D
Original Publication Date: 1995-Oct-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Sethu, H: AUTHOR [+3]

Abstract

Disclosed are multistage interconnection network topologies for systems with 129-512 nodes. The problem solved is that of constructing topologies that achieve the best compromise between multiple and sometimes conflicting objectives such as good performance in terms of bisection bandwidth, easy upgradability from one topology to a larger one, good performance of partitions in the topology, low cost and modularity. The topologies are constructed in a modular fashion using 16-by-16 bidirectional switch boards, each consisting of eight 4-by-4 bidirectional switch chips. In particular, this invention describes two 256-way topologies, referred to as the 256-way Standard and Advantage Options and two 512-way topologies, similarly referred to as 512-way Standard and Advantage Options.

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Multi-Stage Interconnection Network Topologies for Large Systems

      Disclosed are multistage interconnection network topologies for
systems with 129-512 nodes.  The problem solved is that of
constructing topologies that achieve the best compromise between
multiple and sometimes conflicting objectives such as good
performance in terms of bisection bandwidth, easy upgradability from
one topology to a larger one, good performance of partitions in the
topology, low cost and modularity.  The topologies are constructed in
a modular fashion using 16-by-16 bidirectional switch boards, each
consisting of eight 4-by-4 bidirectional switch chips.  In
particular,
this invention describes two 256-way topologies, referred to as the
256-way Standard and Advantage Options and two 512-way topologies,
similarly referred to as 512-way Standard and Advantage Options.

      The basic module based on which all of the topologies are
constructed is a switch board.  Each switch board consists of 8
switch chips, each of which is an 8-input 8-output buffered crossbar
switch.  The switch chip ports are labelled 0 to 7.  The connection
ports on the board are labelled 0 to 31.  Connection port i of a
switch board corresponds to port (i modulo 4) of switch chip i/8.
The connection between the switch chips on a switch board is shown in
Fig. 1.  The same connections may may also be represented as follows
in pseudoC code where "<-->" implies a bidirectional link.
     for (i = 0; i < 4; i++)
   for (j = 4; j < 8; j++)
     {
     port j of switch i <--> port (4+i) of switch (j);
     }

      There are two kinds of notations used in labelling boards in
the specifications of the topologies described here.  NSBs (Node
Switch Boards) are the ones that are directly connected to nodes in
the system.  ISBs (Intermediate Stage Boards) are the ones that are
only connected to other switch boards and not to any nodes.

In all of the following, Node i is assumed...