Chip Existence Determination via Controlling Joint Test Action Group Attention Lines
Original Publication Date: 1995-Oct-01
Included in the Prior Art Database: 2005-Mar-31
Angelotti, FW: AUTHOR [+3]
Adapting to the IEEE standard ATTENTION signal for use in system configuration determination is described.
Chip Existence Determination via Controlling Joint Test
the IEEE standard ATTENTION signal for use in
system configuration determination is described.
determination is one of the earliest tasks during
Power-Up testing. It is desirable to require as little hardware as
possible to be working to perform this task, to minimize the failure
exposures. Also, it is important to have two independent paths for
determining the existence of every card.
configuration can be determined using only the Joint
Test Action Group (JTAG) interface, this involves more logic and code
than would be desired and is still only one path. There are failures
that would make a card look like it did not exist.
JTAG interface is a good exist verification path. A
simple independent configuration determination scheme is also needed.
standard ATTENTION signal can be adapted for use in
system configuration determination.
The function of the IEEE 1149.1 standard
ATTENTION signal was
expanded for configuration determination. When power is first
applied to the chips Built-in Self-Test is run. Upon completion of
this test, every chip activates its ATTENTION signal. If the
ATTENTION signals are unique for each card in the system, it can be
determined which cards exists based on which ATTENTIONs are active.
The IPL activation of the ATTENTION signal need n...