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Horizontally Offset CRT for Direct Current-Coupled Resonant Flyback Deflection Circuits

IP.com Disclosure Number: IPCOM000116701D
Original Publication Date: 1995-Oct-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 223K

Publishing Venue

IBM

Related People

Jackson, FS: AUTHOR

Abstract

The Video Electronics Standards Association (VESA) comprises of an association of several companies in the electronics industry which have an interest in video electronics. VESA now defines widely accepted standards for computer monitor video and sync pulse timings, among others.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 26% of the total text.

Horizontally Offset CRT for Direct Current-Coupled Resonant Flyback
Deflection Circuits

      The Video Electronics Standards Association (VESA) comprises of
an association of several companies in the electronics industry which
have an interest in video electronics.  VESA now defines widely
accepted standards for computer monitor video and sync pulse timings,
among others.

      One such set of VESA timings is for an addressability
(information content) of 1024 x 768 pixels with a refresh rate of 75
Hz, which is sufficient to provide a flicker-free image on most
monitors.  IBM* had previously defined such a standard, but this was
not adopted by VESA for the following reason:

      The IBM standard is known as "XGA-75".  It is designed to run
on IBM's "XGA-2" video adapter card which has a maximum pixel clock
frequency of 90 MHz (90 Mpels/S).  XGA-75 has a pixel clock frequency
of 86 Mhz.  There are, however, several other video adapter cards
available from other manufacturers.  Many of these are limited to a
maximum pixel clock frequency of 80 MHz and are unable to support
IBM's XGA-75 video standard.

      VESA, in an attempt to satisfy market demand for 1024 x 768
addressability with a flicker-free image, and also to satisfy most
video adapter manufacturers, designed their 1024 x 768 @ 75 Hz to run
with a pixel clock frequency of 78.750 MHz - well within the
capability of most video adapter cards on the market.

      VESA's timings, however, did not come without penalty.  In
order to reduce the pixel clock frequency from IBM's 86.000 MHz to
VESA's 78.750 MHz while maintaining the same addressability, both
horizontal and vertical blanking times had to be reduced.  These are
the periods within the horizontal and vertical deflection periods
during which the screen is blanked, and when the electron beams are
returned to their respective starting positions at the left and top
edges of the screen (flyback periods).  Relative to IBM's timings,
VESA reduced horizontal and vertical blanking times by 18.1% and
14.3%, respectively.  While this does not cause difficulties for the
vertical deflection stages of most CRT monitor designs, it does in
fact introduce a very significant problem for their horizontal
deflection circuits.  In designing this mode and its becoming a de
facto standard, VESA solved a problem for the world's video adapter
manufacturers and at the same time created one for its monitor
manufacturers!

Specifically, the problem to the horizontal deflection circuit is as
follows:

      In order to center the displayed image within the bezel in the
horizontal direction, it is necessary to shift the position of the
image within the raster.  This is achieved by introducing an
adjustable phase offset between the incoming horizontal sync pulse
and the deflection circuit's flyback pulse.

      However, in order to have both an acceptable image quality and
adequate phase adjustment range, there must...