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Browse Prior Art Database

Programmable Memory Fault Injection

IP.com Disclosure Number: IPCOM000116702D
Original Publication Date: 1995-Oct-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 139K

Publishing Venue

IBM

Related People

Chan, F: AUTHOR [+6]

Abstract

Disclosed is a method for verifying the functionality of memory test microcode, used to test personal computer system memory, without the use of specialized hardware. With this method, a set of programmable registers, in the DRAM (Dynamic Random Access Memory) memory control ler itself, are used to insert specific pre-selected faults in the DRAM of the computer system. Specifically, these registers are used to program faults into memory before microcode is tested.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Programmable Memory Fault Injection

      Disclosed is a method for verifying the functionality of memory
test microcode, used to test personal computer system memory, without
the use of specialized hardware.  With this method, a set of
programmable registers, in the DRAM (Dynamic Random Access Memory)
memory control ler itself, are used to insert specific pre-selected
faults in the DRAM of the computer system.  Specifically, these
registers are used to program faults into memory before microcode is
tested.

      During the traditional Power-On Self Test (POST) of a personal
computer system, memory diagnostics and operating system memory
manager microcode are responsible for detecting and reporting DRAM
failures.  This process is critical to prevent the corruption of
vital data.  As increasing levels of sophistication are integrated
into DRAM controllers, the development, customization, and especially
the testing of such controllers has grown increasingly complex.
Conventionally, specialized hardware is developed to verify the
functionality of memory test microcode for DRAM controllers.
However, the cost and time needed to develop this specialized
hardware continues to increase.

      To implement the presently-disclosed method, eight registers
have been architected to define two planar DRAM fault injection
functions, which can be expanded to sixteen functions.  These eight
registers are programmed through Index Register Port E0H and Data
Register Port E1H, being selected with indices 0C0H through 0C7H.
Two fault injection functions--parity errors and data compare
errors--are programmed into these registers.  Fig. 1 is a diagram
showing this Index Register Port EOH.

      Fig. 2 is a diagram showing four of these registers, Diagnostic
Address Registers A-D, which are used to specify the memory address
at which a memory fault is to be injected.  This configuration drives
up to 32 address bits.

      Fig. 3 is a diagram showing two of these registers, Diagnostic
Command Registers A and B.  In Command Register A, bits 0-3 indicate
whether parity errors or data compare errors are to be injected, and
bits 4-7 enable these functions for the high or low byte of data, or
disable these functions.

      Fig. 4 is a...