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Fault Isolation and Reconfiguration in a Communication Controller with Distributed Processing

IP.com Disclosure Number: IPCOM000116706D
Original Publication Date: 1995-Oct-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 166K

Publishing Venue

IBM

Related People

Aquaronne, E: AUTHOR [+4]

Abstract

Disclosed is a hardware and microcode mechanism for automatic fault isolation and reconfiguration in a communication controller with distributed processing.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 34% of the total text.

Fault Isolation and Reconfiguration in a Communication Controller
with Distributed Processing

      Disclosed is a hardware and microcode mechanism for automatic
fault isolation and reconfiguration in a communication controller
with distributed processing.

      The current structure of a communication controller is to
interconnect microprocessor based adapters through a switch (Figure).
Each adapter attaches communication lines and, when required,
messages are exchanged between adapters accross the switch.

      To provide high availability the adapters are duplicated with
the capability to automatically fallback all the communication lines
of a given adapter to the back-up adapter.

      A fault can occur in the switch itself, in an adapter (due to
hardware or to microcode) or in the interface between the switch and
an adapter.  The purpose of the described mechanism is to detect
errors which prevent an adapter to work or to exchange messages via
the switch and to isolate the fault into the switch or into a given
adapter.  This isolation is required to perform the appropriate
reconfiguration and schedule the maintenance with the required part.

Structure - The switch provides Clocks (CK) to its own logic and to
the various adapters, has a Switch Control (SC) able to receive
requests for connection from as many Switch Interface (SI) as there
are attached adapters.  The SC schedules the connection to the
requested adapter and, once acknowledged, grants the connection to
the requesting adapter.  Once the connection is established, a Data
Module (DM) switches, by bursts of 32 bytes, a message from an
adapter to another.

      Each adapter attaches to the switch via a Switch Adapter (SA).
The SA receives clock signal from the switch, has a control interface
to request connection with another adapter and to be notified of a
connection request from another adapter and also a data interface to
send/receive data.  The Central Part (CP) of the adapter includes the
microprocessor, storage and interface to the communication lines.

      A Service Logic (SL), in the switch as well as in each adapter
stores error information and is accessible via the service bus from a
the special adapter which attaches the Service Processor (SP).  This
special adapter is called SP adapter.

Types of errors

Switch - Hardware checkers in the switch detects the following
errors:
  1.  In the CK logic: master oscillator, clock signals and clock
       drivers error.
  2.  In the SC logic: scheduler error and parity error on requests
for
       connection.
  3.  In the DM logic: invalid adapter address for data switching.
  4.  In the SI: synchronization error and drivers error.

When the fault is inside a central function of the switch (CK logic
or scheduler error in the SC logic), the entire communication
controller is impacted.  As opposed, for all other switch faults, a
single adapter is impacted.  But even when only...