Browse Prior Art Database

Random Avplist Generator

IP.com Disclosure Number: IPCOM000116717D
Original Publication Date: 1995-Oct-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 136K

Publishing Venue

IBM

Related People

Glenn, SC: AUTHOR

Abstract

The System Simulation and Verification methodology for RISC-based microprocessors uses manually written testcase programs or ivps, Implementation Verification Programs, to functionally verify, through simulation, DSL-compiled designs. A list of ivps and their simulation or run-time parameters are contained in a text formatted file called an avplist. There are one or more avplists per functional area of a design and these avplists comprise an ivp plan. Each avplist contains a sequential list of ivps that are run or regressed time and time again in the same order as new or updated simulation models become available from designers. Since the ivps are run sequentially, there is no variation or randomness to the simulation of testcases and thus, a predictable pattern of test case runs will exist every time.

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Random Avplist Generator

      The System Simulation and Verification methodology for
RISC-based microprocessors uses manually written testcase programs or
ivps, Implementation Verification Programs, to functionally verify,
through simulation, DSL-compiled designs.  A list of ivps and their
simulation or run-time parameters are contained in a text formatted
file called an avplist.  There are one or more avplists per
functional area of a design and these avplists comprise an ivp plan.
Each avplist contains a sequential list of ivps that are run or
regressed time and time again in the same order as new or updated
simulation models become available from designers.  Since the ivps
are run sequentially, there is no variation or randomness to the
simulation of testcases and thus, a predictable pattern of test case
runs will exist every time.  This is very unlikely with a finished
product.

      Generally, the ivps contained within the avplists are simulated
with a run-time parameter called forced reset.  This parameter
essentially cold starts the system model before the simulation of the
next sequential ivp in the avplist, thereby resetting latches, state
machines, and buffers for each ivp.  Although, this parameter allows
the system debugger to easily isolate a logic flaw to a given ivp, it
does not provide for a collective environment.

      A method or tool must exist to allow avplists or multiple
avplists to be regressed in a non-sequential order and regressed
without the forced reset parameter to allow ivps to run in an unknown
or non-initialized  state of the machine.  If not, design flaws could
be concealed.

      The Random Avplist Generator (RAG), a REXX-based tool, was
developed to solve the problem of sequential regressions by
generating a random avplist from source avplists, and then submitting
the new avplist for simulation.  Source avplists are obtained from
each microprocessor component's ivp plan.

      Basically, RAG accepts up to two source avplists and randomly
chooses ivps from the avplist or  avplists, appends the ivps to a
temporary avplist until all ivps have been selected,  and finally
submits the new avplist in small packets to a simulation cluster via
a Q-Man downloader (Fig. 1).  Standard reporting tools, such as
ivreport, are used for the verification and tracking of ivps for each
ivp plan.

FUNCTIONAL DESCRIPTION - RAG consists of several internal
subroutines and uses a pre-existing submission tool to allow users
the greatest flexibility as possible.  The description of these
subroutines can be found in the following section.  Fig. 2 contains a
general program flow overview.  RAG exits when all ivps have been
selected and submitted.

INVOKATION - RAG is invoked by the following command:
  rag <avplist1>(<avplist2>) (opts
  where:    avplist1 = filename of the source avplist containing ivps
            avplist2 = optional.  A second source avplist.
         ...