Browse Prior Art Database

Use of 8-bit First-in, First-out with 16-bit Microprocessor

IP.com Disclosure Number: IPCOM000116719D
Original Publication Date: 1995-Oct-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 95K

Publishing Venue

IBM

Related People

Benayoun, A: AUTHOR [+3]

Abstract

When a 16-bit microprocessor needs an external First-in, First-out (FIFO) on the card, the designer can either use one 16-bit FIFO or two 8-bit FIFO's (one for the low byte and another one for the high byte). The best solution from a cost point of view, would be to only use one 8-bit FIFO to interface a 16-bit microprocessor data bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Use of 8-bit First-in, First-out with 16-bit Microprocessor

      Hardware Design

      When a 16-bit microprocessor needs an external First-in,
First-out (FIFO) on the card, the designer can either use one 16-bit
FIFO or two 8-bit FIFO's (one for the low byte and another one for
the high byte).  The best solution from a cost point of view, would
be to only use one 8-bit FIFO to interface a 16-bit microprocessor
data bus

The advantages of the current solution are the following:
  o  Only one 8-bit FIFO in the design
  o  Low cost design

Applications of the invention:
  o  Any hardware design requiring FIFOs within a 16-bit
      microprocessor environment

      Principle of Operation for a Write FIFO Operation The timing
for a write operation is given hereafter.

Principle of operation:
  1.  The microprocessor starts its write cycle by generating the
       FIFO address during T1.  This address is internally latched
       and decoded by a Peripheral Chip Select (-PCSx) signal.
  2.  The microprocessor activates its write command (-WR) signal in
T2
       and puts the 16-bit data to be stored in the FIFO on its data
       bus.
  3.  When the -PCSx signal is active the control logic desactivates
       the ready (RDY) signal for 3 clocks.  Therefore, the
       microprocessor is forced to insert one wait state (Tw) during
its
       write cycle.
  4.  When the -WR signal is active the control logic generates a
       one-clock width signal (-OEWL) during T2 and another one
(-OEWH)
       during Tw.  The -OEWL signal enables the driver that provides
the
       low data byte D0-7 to the input FIFO data bus.  The -OEWH
signal
       enables the driver that provides the high data byte D8-15 to
the
       input FIFO data bus.
  5.  The FIFO write signal (-FFWR) is the sum of the -OEWL and -OEWH
       signals.  Therefore the low data byte D0-7 is stored in the
FIFO
       during T2 and the high data byte D8-15 is stored in the FIFO
       during Tw.
  6.  The microprocessor terminates its write cyc...