Browse Prior Art Database

Resource Management for Non-Micro Channel DMA Masters

IP.com Disclosure Number: IPCOM000116731D
Original Publication Date: 1995-Oct-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 143K

Publishing Venue

IBM

Related People

Lyons, ME: AUTHOR [+2]

Abstract

A method for efficient AIX* device driver management of resources needed to do Bus Master DMA on non-Micro Channel* buses is disclosed. The device driver manipulates the mapping data structure prior to calls to the AIX DMA kernel services.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 45% of the total text.

Resource Management for Non-Micro Channel DMA Masters

      A method for efficient AIX* device driver management of
resources needed to do Bus Master DMA on non-Micro Channel* buses is
disclosed.  The device driver manipulates the mapping data structure
prior to calls to the AIX DMA kernel services.

      For non-Microchannel buses, the AIX kernel provides a service
(D_MAP_LIST) that takes as its input a list of virtual buffer
addresses, sizes, and cross-memory address space descriptors.
D_MAP_LIST returns a list of bus addresses and lengths to then be
used by the DMA master device.  This return list is typically called
a "scatter-gather" list.

      In order to increase i/o through-put, it is desirable to allow
a DMA master to process more than one data transfer request at a
time.  This introduces a problem in how to efficiently manage the
mapping data structure(s) and "scatter-gather" list(s).  Reserving 1
mapping data structure per i/o is inefficient for a variety of
reasons.

      The solution is to utilize only 1 mapping data structure per
DMA master device.  This approach reduces resource utilization by
decreasing the amount of pages required to support the device and
reducing the number of pages that must be mapped.  I/O throughput is
also enhanced by simplifying the processing that the DMA master
incurs
in identifying and locating the various scatter-gather list entries.

      In order to only use 1 mapping data structure, the device
driver code supporting the DMA master must manipulate the mapping
data structure before calling the D_MAP_LIST service.  The mapping
data structure contains 3 fields that pertain to this discussion:

TOTAL_IOVECS - the number of vectors available to be used in the
mapping (i.e., to be filled in with bus address/length/xmem vectors)
This is filled out by the device driver.

DVEC - this points to the first available vector to be used in the
mapping.  This is set by the device driver.  The D_MAP_LIST service
begins writing the mapped vectors at this location.

USED_IOVECS - the number of vectors used when the actual mapping is
performed.  This will be less than or equal to TOTAL_IOVECS.  It is
filled out by the D_MAP_LIST code.

The algorithm consists of the following steps:
  1.  The device driver allocates a single mapping structure when the
       DMA master device is first opened.  The area of memory pointed
to
       by the DVEC field must be large enough to hold enough mapping
       vectors to support the DMA master device's maximum transfer
size
       (in the worst-case, each vector will map one page of memory).
  2.  If the DMA master device requires it, the device driver
       identifies the page(s) of memory pointed to by DVEC.  This may
       require the device driver to map the page(s) pointed to by
DVEC
       first.  The device driver performs any microcode
initialization
       to allow the DMA master su...