Browse Prior Art Database

Clock Synchronization Method Speeds Processor Access to Memory

IP.com Disclosure Number: IPCOM000116753D
Original Publication Date: 1995-Nov-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Karp, JM: AUTHOR [+2]

Abstract

A method for synchronizing microprocessors with memory control logic is disclosed. The method uses the internal phase-lock-loop of the processor to synchronize to the memory controller allowing improved access speeds to memory.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 57% of the total text.

Clock Synchronization Method Speeds Processor Access to Memory

      A method for synchronizing microprocessors with memory control
logic is disclosed.  The method uses the internal phase-lock-loop of
the processor to synchronize to the memory controller allowing
improved access speeds to memory.

      Microprocessors need to access DRAM, SRAM, registers and other
periperals which are inherently asynchronous devices.  The logic
which controls this access and generates the necessary timing
signals, for example a DRAM controller, must accept processor signals
synchronized to the processor clock and generate the required signals
for the peripherals.  The problem is that this sync logic, such as a
DRAM controller, typically resides in a large VLSI module and cannot
run directly from the processor clock for these reasons:
  o  The circuits are LSSD circuits requiring special clocks which
      must be generated from the processor clock.
  o  The processor clock feeds many latches and there are significant
      delays in fan-out and re-drive networks.  Additionally, this
      delay varies with voltage, temperature, and process.

      The method disclosed here solves these problems by outputting
a synchronization clock from the VLSI module and phase locking the
processor to this clock using the internal PLL.  A block diagram of
this method is shown in the Figure which uses the Intel 80960
processor.  In this system, the raw 40Mhz oscillator...