Browse Prior Art Database

Linescan Video Pre-Processor for use in Optical Analysis

IP.com Disclosure Number: IPCOM000116759D
Original Publication Date: 1995-Nov-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 113K

Publishing Venue

IBM

Related People

Lisanke, M: AUTHOR [+2]

Abstract

Disclosed is a pre-processor for sorting through data arriving in real time, at a rate of 20 million points per second, from a linescan Charge Coupled Device (CCD) camera following the scan of a hardfile disk in a spiral path while being illuminated with an interferometer. Using laser darkfield shear length interferometry, this technique yields darkness across smooth areas of the disk, while defects appear as spots of brightness. Typically, the vast majority of the disk is recorded as blackness, indicating that the disk is within desired limits. Scanning a typical 95-mm (millimeter) diameter disk results in approximately 460 Mbytes (megabytes) of data, almost all of which consists of null data points.

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Linescan Video Pre-Processor for use in Optical Analysis

      Disclosed is a pre-processor for sorting through data arriving
in real time, at a rate of 20 million points per second, from a
linescan Charge Coupled Device (CCD) camera following the scan of a
hardfile disk in a spiral path while being illuminated with an
interferometer.  Using laser darkfield shear length interferometry,
this technique yields darkness across smooth areas of the disk, while
defects appear as spots of brightness.  Typically, the vast majority
of the disk is recorded as blackness, indicating that the disk is
within desired limits.  Scanning a typical 95-mm (millimeter)
diameter disk results in approximately 460 Mbytes (megabytes) of
data, almost all of which consists of null data points.  Thus, the
pre-processor stores the valuable data with tags locating each datum
on the disk surface, while discarding the null data.

      The video pre-processor consists of three main parts---a Video
Processing Board (VPB), a log (position logging) card, and a Digital
Signal Processor (DSP) card.

      Fig. 1 is a block diagram of the VPB 8, which functions as a
controller for the CCD camera 9, and which processes returning video
data.  Camera clocking and timing circuits 10 generate a 20-megahertz
clock signal and a line synch pulse every 1063 clock cycles, which
causes the camera 9 to take a snapshot of the current view and to
begin transferring data to the VPB.  This number of clock cycles
matches the 1063 pixel elements in the CCD array, of which 1024 are
active, containing valid data.  The remaining pixel elements contain
control and video information, which is not valid data, and which is
stripped away by the VPB.

      When this data reaches the VPB 8, it travels through analog
circuitry 14, to be digitized in an analog to digital converter 16
before being delivered to a comparator 18, where the data is compared
to a threshold representing the video signal level predetermined to
be equivalent to the smallest feature of interest.  If the data is
below that threshold level, the data is discarded, and a single point
is sent at the end of each scan to serve as a synchronization pulse.
If the data level exceeds the threshold level, the pixel number of
the data element at which the threshold level is exceeded is stored
in a First In, First Out (FIFO) memory 20.  Various operations of the
analog to digital converter 16, the comparator 18, and the FIFO
memory 20 are controlled by timing and control circuits 21.

      The values of subsequent pixels are compared with the level
stored in the FIFO memory 20.  If the new value is greater, the
stored value is replaced with the new value.  ...