Browse Prior Art Database

Intersystem Channel State Encoding Optimized for a Microprocessor

IP.com Disclosure Number: IPCOM000116770D
Original Publication Date: 1995-Nov-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 109K

Publishing Venue

IBM

Related People

Gregg, TA: AUTHOR [+4]

Abstract

Disclosed is a method for the implementation of a microcode driven state machine used to process incoming frames in a serial communications link. The encoding of the various states is chosen to allow the fastest processing of the most performance critical functions by a RISC microprocessor. The less performance critical functions involve the use of a null state that forces the microcode to use a slower decoding of the more compactly encoded additional states.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Intersystem Channel State Encoding Optimized for a Microprocessor

      Disclosed is a method for the implementation of a microcode
driven state machine used to process incoming frames in a serial
communications link.  The encoding of the various states is chosen to
allow the fastest processing of the most performance critical
functions by a RISC microprocessor.  The less performance critical
functions involve the use of a null state that forces the microcode
to use a slower decoding of the more compactly encoded additional
states.

      This disclosure relates to the message channel described (1).
While a hardware implementation of this disclosure is described in
(2), this disclosure describes a code implementation including error
processing.  In this message channel, the exchange of frames consists
of a Message Command Block (MCB) sent by a sender channel at one end
of the link, followed by a Message Response Block (MRB) returned by a
receiver channel at the other end of the link.  Slightly more
complicated exchanges send DATA frames.  For a write operation, the
sender channel transmits a DATA frame after the MCB, and for a read
operation the receiver channel transmits a DATA frame before the MRB.
It is the primary design goal of this channel to perform the frame
exchanges described above as quickly as possible.  This channel also
allows exchanges of multiple DATA frames within a single operation
and handles link bit error recovery.  These operations are
considerably more complicated than the operations described earlier,
and it is not a requirement to perform them quickly.

      As each frame is received, it examined my the microprocessor.
The microprocessor uses state information for the particular buffer
set to determine if the proper frame is received at the proper time.
During link bit error recovery, these states help determine which
frame is in error and monitor the progress of the recovery procedure.
If a frame is not received in the proper order, either the sender is
in error or a previous frame may have been lost.  In either case,
information has not been properly exchanged, and further recovery
actions are required.

      The choice for the encoding of the state information determines
how quickly it can be accessed by a particular type of
microprocessor, and in this disclosure a RISC microprocessor is used.
The fastest test that the microprocessor can perform is a branch
based on the value of a single bit of a register.  So, each of the
performance critical states is represented by a single bit of a
multiple bit field.  The Figure shows the bit assignments in which
the first three bits are used for the performance critical states
(IDLE, DATA START, and DATA END).  Normally, exactly one of the bits
is on indicating the present state.  Two or more bits are never on.
In addition to the performance critical states, there are many less
performance critical states represented by bits 3 through 15 in t...