Browse Prior Art Database

Shared Burst Sequence Generator

IP.com Disclosure Number: IPCOM000116791D
Original Publication Date: 1995-Nov-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 90K

Publishing Venue

IBM

Related People

Hosokawa, K: AUTHOR

Abstract

Disclosed is a Shared Burst Sequence Generator Circuit for a synchronous DRAM which functions variable order of burst data sequence. This circuit realizes fast address data out with minimum circuit area.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Shared Burst Sequence Generator

      Disclosed is a Shared Burst Sequence Generator Circuit for a
synchronous DRAM which functions variable order of burst data
sequence.  This circuit realizes fast address data out with minimum
circuit area.

      The burst sequence generator consists of five circuits, ADDRESS
LATCH, BIT COUNTER, SEQUENCE OUT BIT-0, SEQUENCE OUT BIT-1 and
SEQUENCE OUT BIT2.  Fig. 1 shows this block diagram.  The ADDRESS
LATCH circuit is shown in Fig. 2.  This circuit holds first column
address, namely, first address of the burst sequence by 'SET' low
pulse.  Fig. 3 is BIT COUNTER.  This circuit has seven shift
registers named SFTR0-6.  A complement output of the SFTR0 is
connected to its input.  Therefore, output 'A' generates pulses which
have a half frequency of 'SFTCLK'.  SFTR1 and SFTR2 are two cascaded
connections, and inverted output is connected to the first stage
input.  A half frequency of 'A' appears at 'B' and 'C'.
SFTR3,SFTR4,SFTR5 and SFTR6 make four cascaded connections with final
complement data feedbacking.  So 'D', 'E','F','G' are generated a
frequency one eighth of the 'SFTCLK'.  Each shift register has
resister initialize function.  'SET' negative pulse which is issued
at CAS command timing, sets each output of the shift resister to
zero.  Therefore, the output nodes 'A','B','C','D','E','F' and 'G'
are transferred by clock 'SFTCLK' as shown in Table 1.

      The SEQUENCE OUT BIT-0 circuit is shown in Fig. 4. ...