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Browse Prior Art Database

Digital Phase-Locked Logic Adaptive Threshold Circuit

IP.com Disclosure Number: IPCOM000116844D
Original Publication Date: 1995-Nov-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 6 page(s) / 123K

Publishing Venue

IBM

Related People

Kelley, PE: AUTHOR [+3]

Abstract

Digital Phase-Locked Logic (DPLL) performs a clock recovery function in communication networks. It also can provide the link performance information.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Digital Phase-Locked Logic Adaptive Threshold Circuit

      Digital Phase-Locked Logic (DPLL) performs a clock recovery
function in communication networks.  It also can provide the link
performance information.

      The DPLL uses a histogram counter to collect digital data
timing jitter information.  A threshold circuit detects an eye
opening from the timing jitter histogram.  This eye opening can be
used to select the optimum clock phase for the data regeneration or
measure the data link timing jitter.  The DPLL histogram counter
threshold is usually fixed.  However, the fixed threshold level needs
to be optimized for a particular data jitter level and jitter
statistical distribution of the communication link.  If it is not
done properly, it could result in phase offset error and increase
data Bit Error Rate (BER).  This is also a time consuming process
which
would have to be done for each application the DPLL is used with.

      Described is an Adaptive Threshold Circuit which automatically
adjusts the histogram counter threshold level for a particular timing
jitter statistical distribution and jitter level.  It also reduces
the number of circuits needed to build the DPLL histogram counter.

      The histogram counter stores the number of the data edge sorts
corresponding to a particular time slot.  The DPLL histogram counter
threshold level is typically fixed.  It is optimized for a particular
data timing jitter level and statistical distribution.  It limits a
particular DPLL design for a particular application.  It also
requires
an extensive testing and threshold adjustment for the DPLL
optimization.

      The DPLL histogram counter threshold circuit converts the two
dimensional timing jitter histogram into one dimensional binary word.
Fig. 1 shows a typical histogram.  The vertical axis represents the
number of data edge samples in the particular time slot.  The
horizontal axis represents eight sorting time slots.  The number of
slots depends on the required resolution.  The histogram time slot
reading that exceeds the threshold is converted into the binary 1.
The histogram time slot reading that falls below the threshold is
converted into the binary 0.  Fig. 1 shows three fixed threshold
levels.  Depending on the fix threshold level, the conversion result
will vary.  To achieve the best data BER, the regenerative clock
phase has to be selected at the absolute minimum of data sort
histogram.  Threshold 2 provides the optimum clock phase selection.
If fixed threshold 3 is fixed too high, the selection will cause a
recovered clock phase offset.  If threshold 1 is selected too low, it
decodes the data sort...