Browse Prior Art Database

Direct Access Storage Device Compression and Decompression Data Flow

IP.com Disclosure Number: IPCOM000116855D
Original Publication Date: 1995-Nov-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 6 page(s) / 169K

Publishing Venue

IBM

Related People

Moertl, DF: AUTHOR [+3]

Abstract

An effective, reliable, and low latency data flow for outboard data compression and decompression between a Central Processing Unit's (CPU) memory and fixed block direct access storage device (DASD) is described. The compression I/O Processor (IOP) offloads the CPU by compressing 4K-byte pages from main memory into multiple 512-byte DASD sectors. The IOP manages the placement of these sectors on the DASD and provides a smooth data flow between the DASD and the CPU's main memory. The IOP achieves a higher compression ratio than other implementations by splitting a write into multiple blocks and evaluating the compression efficiency of each block. If a block increases in size after being compressed, then the raw data block is stored.

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Direct Access Storage Device Compression and Decompression Data Flow

      An effective, reliable, and low latency data flow for outboard
data compression and decompression between a Central Processing
Unit's (CPU) memory and fixed block direct access storage device
(DASD) is described.  The compression I/O Processor (IOP) offloads
the CPU by compressing 4K-byte pages from main memory into multiple
512-byte DASD sectors.  The IOP manages the placement of these
sectors on the DASD and provides a smooth data flow between the DASD
and the CPU's main memory.  The IOP achieves a higher compression
ratio than other implementations by splitting a write into multiple
blocks and evaluating the compression efficiency of each block.  If a
block increases in size after being compressed, then the raw data
block is stored.

      The data to be compressed consists of one or more host pages.
A host page has a 64-byte tag field and 4096-byte data field.
Uncompressed data would be stored on DASD in 8 520-byte sectors with
each sector containing 8-bytes from the tag and 512-bytes from the
data.  An extra two-byte check field would be added to the end of
each sector to form a 522-byte DASD sector.  This design does not
change the DASD sector size.

      Fig. 1 shows the components of a computer 10 with this
invention.  The CPU 11 has raw uncompressed tags 13 and data 14
stored in main memory 12 that it needs compressed and written to DASD
30.  The raw data consists of multiple 4096-byte host pages with
64-bytes of tags for each host page.  The CPU 11 instructs the IOP 15
which one or more host pages to write.

      The IOP 15 will compress each host page, 64-bytes of tags and
4096-bytes of data, into as few 512-byte sectors as possible.  An
example of a 3-sector compressed output is shown in Fig. 2.  The
first four bytes of the first sector 32 will be a compression check
field.  The compression check field consists of a two-byte Cyclic
Redundancy Code (CRC) 35 and a two-byte length field 36.  The CRC is
generated over the entire host page.  The length field includes the
compression check field, it is equal to the length of the compressed
data plus four.  The last 512-byte sector 34 will be padded 38 with
data (zeros or random data) to the 512-byte boundary.

      The smallest output of the compressor 16 would have a length of
51-bytes, 1 sector.  The largest output would have a length of
5204-bytes, 11 sectors.  When there is compression growth, the length
of the compressed host page is larger than 8 sectors (4096-bytes),
the compressor 16 will just copy the raw data into a 9-sector output
shown in Fig. 3.  The first sector has the four-byte compression
check field, with the length field 51 is set to a fixed key value,
followed by the 64-bytes of tags 52 and 444-bytes of pad 53.  The
following eight sectors 42-49 are just the 4096-bytes of data 54 from
the host page that was copied.  This offers improved compression
e...