Browse Prior Art Database

Gate Drive of Complimentary FET PWM Amplifier

IP.com Disclosure Number: IPCOM000116868D
Original Publication Date: 1995-Nov-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 91K

Publishing Venue

IBM

Related People

Bahr, AA: AUTHOR [+3]

Abstract

This paper describes a self-powered gate-voltage power supply used in a low voltage complimentary FET switch mode servo amplifier. The amplifier load is operated in fully regenerative continuous conduction mode, with PWM gate drive applied to both top (P-channel) and bottom (N-channel) FETs of the bridge.

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Gate Drive of Complimentary FET PWM Amplifier

      This paper describes a self-powered gate-voltage power supply
used in a low voltage complimentary FET switch mode servo amplifier.
The amplifier load is operated in fully regenerative continuous
conduction mode, with PWM gate drive applied to both top (P-channel)
and bottom (N-channel) FETs of the bridge.

      This paper describes a method of supplying power to FET gate
driver circuits used to drive the high-side P-channel devices of a
PWM bridge servo amplifier.  This approach is limited to power supply
voltages between 20 and 40 volts, where half the power supply voltage
is more than the FET V(gs) threshold, yet less than the V(gs)
breakdown.

      The technique was applied to the reel motor servo amplifiers of
a tape drive which demanded four-quadrant, fully regenerative,
control of motor armature current.  This type of PWM operation
demands
simultaneous pulsewidth modulation of both top and bottom FET
switches.

      FET gate drive peak currents typically exceed one ampere, so a
low impedance power source is required by the gate driver integrated
circuits.  This technique establishes a third power supply rail
floating half way between the positive and ground rails (hereafter,
referred to as Mid-Rail) (Figure).

      Only one half of the H-Bridge power amplifier is shown in the
Figure.

      Each FET gate is driven by a commercially available
ground-referenced gate driver chip typically designed for operation
of a DC-DC converter.  The P-channel top side FET gate drivers are
powered between the High Rail (+36 Vdc in this particular
application), and Mid-Rail (which is +18 Vdc, half the difference
between high- and ground-rails).  Thus, the V(gs) of the P-channel
FET cannot exceed 18 volts.

      The low side N-channel FET gate drivers are powered between
Mid-Rail (still at +18 Vdc) and Ground Rail.  Again, the V(gs) of the
N-channel FET's cannot exceed +18 Vdc, or half the value of the +36
Vdc High Rail.

      When PWM is applied to a diagonally opposite N- and P-channel
pair of FET switches, the net charge delivered and removed from
Mid-Rail is nearly balanced.  For example, turning the upper left
P-channel FET on will remove charge from the FET gate capacitor and
dump it...